W948D6FBHX5E-TR Datasheet, PDF (4/60 Pages) Winbond – 256Mb Mobile LPDDR

W948D6FB / W948D2FB
256Mb Mobile LPDDR
1. GENERAL DESCRIPTION
W948D6FB / W948D2FB is a high-speed Low Power double data rate synchronous dynamic random access
memory (LPDDR SDRAM), An access to the LPDDR SDRAM is burst oriented. Consecutive memory location in one
page can be accessed at a burst length of 2, 4, 8 and 16 when a bank and row is selected by an ACTIVE command.
Column addresses are automatically generated by the LPDDR SDRAM internal counter in burst operation. Random
column read is also possible by providing its address at each clock cycle. The multiple bank nature enables
interleaving among internal banks to hide the pre-charging time. By setting programmable Mode Registers, the
system can change burst length, latency cycle, interleave or sequential burst to maximize its performance. The
device supports special power saving functions such as Partial Array Self Refresh (PASR) and Automatic
Temperature Compensated Self Refresh (ATCSR).
2. FEATURES
 VDD = 1.7~1.95V
 VDDQ = 1.7~1.95V
 Data width: x16 / x32
 Clock rate: 200MHz(-5),166MHz (-6), 133MHz (-75)
 Partial Array Self-Refresh(PASR)
 Auto Temperature Compensated Self-Refresh(ATCSR)
 Power Down Mode
 Deep Power Down Mode (DPD Mode)
 Programmable output buffer driver strength
 Four internal banks for concurrent operation
 Data mask (DM) for write data
 Clock Stop capability during idle periods
 Auto Pre-charge option for each burst access
 Double data rate for data output
 Differential clock inputs (CK and CK )
 Bidirectional, data strobe (DQS)
 CAS Latency: 2 and 3
 Burst Length: 2, 4, 8 and 16
 Burst Type: Sequential or Interleave
 64 ms Refresh period
 Interface: LVCMOS
 Support package:
60 balls VFBGA (x16)
90 balls VFBGA (x32)
 Operating Temperature Range
Extended (-25°C to + 85 °C)
Industrial (-40°C to + 85 °C)
Publication Release Date : Oct, 15, 2012
-4-
Revision : A01-004