W948D6FBHX5E-TR Datasheet, PDF (49/60 Pages) Winbond – 256Mb Mobile LPDDR

W948D6FB / W948D2FB
256Mb Mobile LPDDR
(256Mb, X32)
PARAMETER SYMBOL
TEST CONDITION
-5
Operating one
bank active-
precharge
current
IDD0
tRC = tRCmin ; tCK = tCKmin ; CKE is HIGH; CS is
HIGH between valid commands; address inputs are ⁴⁰
SWITCHING; data bus inputs are STABLE
Precharge
power-down
standby current
Precharge
power-down
standby current
with clock stop
IDD2P
IDD2PS
Low
all banks idle, CKE is LOW; CS is HIGH, _power
0.3
tCK = tCKmin ; address and control inputs are _Normal
SWITCHING; data bus inputs are STABLE
power
0.4
all banks idle, CKE is LOW; CS is HIGH, CK ^Low
power
0.3
= LOW, CK = HIGH; address and control
inputs are SWITCHING; data bus inputs are
STABLE
Normal
power
0.4
Precharge non
power-down
standby current
Precharge non
power-down
standby current
with clock stop
IDD2N
IDD2NS
all banks idle, CKE is HIGH; CS is HIGH, tCK =
tCKmin; address and control inputs are SWITCHING; ¹⁰
data bus inputs are STABLE
all banks idle, CKE is HIGH; CS is HIGH, CK = LOW,
CK = HIGH; address and control inputs are ³
SWITCHING; data bus inputs are STABLE
Active power-
down standby
current
IDD3P
one bank active, CKE is LOW; CS is HIGH, tCK =
tCKmin; address and control inputs are SWITCHING; ³
data bus inputs are STABLE
Active power-
one bank active, CKE is LOW; CS is HIGH, CK = LOW,
down standby
current with clock
IDD3PS
CK = HIGH; address and control inputs are ³
stop
SWITCHING; data bus inputs are STABLE
Active non
power-down
standby current
Active non
power-down
standby current
with clock stop
IDD3N
IDD3NS
one bank active, CKE is HIGH; CS is HIGH, tCK =
tCKmin; address and control inputs are SWITCHING; ²⁵
data bus inputs are STABLE
one bank active, CKE is HIGH; CS is HIGH, CK =
LOW, CK = HIGH; address and control inputs are ¹⁵
SWITCHING; data bus inputs are STABLE
Operating burst
read current
IDD4R
one bank active; BL = 4; CL = 3; tCK = tCKmin ;
continuous read bursts; IOUT = 0 mA; address inputs are 75
SWITCHING; 50% data change each burst transfer
Operating burst
write current
Auto-Refresh
Current
IDD4W
IDD5
one bank active; BL = 4; t CK = tCKmin ; continuous write
bursts; address inputs are SWITCHING; 50% data 55
change each burst transfer
tRC = tRFCmin ; tCK = tCKmin ; burst refresh; CKE is
HIGH; address and control inputs are SWITCHING; data 50
bus inputs are STABLE
- 6 - 75 UNIT
38
35 mA
0.3 0.3
mA
0.4 0.4
0.3 0.3
mA
0.4 0.4
10
10 mA
3
3
mA
3
3
mA
3
3
mA
20
20 mA
12
12 mA
70
70 mA
50
50 mA
50
50 mA
Deep Power-
Down current
IDD8(4)
Address and control inputs are STABLE; data bus inputs
are STABLE
10
10
10
uA
Notes:
1. IDD specifications are tested after the device is properly initialized.
2. Input slew rate is 1V/ns.
3. Definitions for IDD:
LOW is defined as VIN ≤ 0.1 * VDDQ;HIGH is defined as VIN ≥ 0.9 * VDDQ;STABLE is defined as inputs stable at a HIGH or LOW level;
SWITCHING is defined as:
- Address and command: inputs changing between HIGH and LOW once per two clock cycles;
- Data bus inputs: DQ changing between HIGH and LOW once per clock cycle; DM and DQS are STABLE.
4. IDD8 is a typical value at 25°C.
- 49 -
Publication Release Date : Oct, 15, 2012
Revision : A01-004