W948D6FBHX5E-TR Datasheet, PDF (48/60 Pages) Winbond – 256Mb Mobile LPDDR

W948D6FB / W948D2FB
8.4 IDD Specification Parameters and Test Conditions
8.4.1 IDD Specification Parameters and Test Conditions
[Recommended Operating Conditions; Notes 1-3]
(256Mb, X16)
256Mb Mobile LPDDR
PARAMETER SYMBOL
TEST CONDITION
-5
Operating one
bank active-
precharge
current
IDD0
tRC = tRCmin ; tCK = tCKmin ; CKE is HIGH; CS is HIGH
between valid commands; address inputs are ⁴⁰
SWITCHING; data bus inputs are STABLE
Precharge
power-down
standby current
Precharge
power-down
standby current
with clock stop
IDD2P
IDD2PS
all banks idle, CKE is LOW; CS is HIGH, tCK
Low
power
0.3
= tCKmin ; address and control inputs are _Normal
SWITCHING; data bus inputs are STABLE
power
0.4
all banks idle, CKE is LOW; CS is HIGH, CK = ^Low
power
0.3
LOW, CK = HIGH; address and control inputs Normal
are SWITCHING; data bus inputs are STABLE power
0.4
Precharge non
power-down
standby current
Precharge non
power-down
standby current
with clock stop
IDD2N
IDD2NS
all banks idle, CKE is HIGH; CS is HIGH, tCK = tCKmin;
address and control inputs are SWITCHING; data bus ¹⁰
inputs are STABLE
all banks idle, CKE is HIGH; CS is HIGH, CK = LOW,
CK = HIGH; address and control inputs are
3
SWITCHING; data bus inputs are STABLE
Active power-
down standby
current
Active power-
down standby
current with
clock stop
IDD3P
IDD3PS
one bank active, CKE is LOW; CS is HIGH, tCK =
tCKmin;address and control inputs are SWITCHING; data ³
bus inputs are STABLE
one bank active, CKE is LOW; CS is HIGH, CK = LOW,
CK = HIGH; address and control inputs are
3
SWITCHING; data bus inputs are STABLE
Active non
power-down
standby current
Active non
power-down
standby current
with clock stop
Operating burst
read current
IDD3N
IDD3NS
IDD4R
Operating burst
write current
IDD4W
Auto-Refresh
Current
Deep Power-
Down current
IDD5
IDD8(4)
one bank active, CKE is HIGH; CS is HIGH, tCK =
tCKmin; address and control inputs are SWITCHING; data ²⁵
bus inputs are STABLE
one bank active, CKE is HIGH; CS is HIGH, CK = LOW,
CK = HIGH; address and control inputs are ¹⁵
SWITCHING; data bus inputs are STABLE
one bank active; BL = 4; CL = 3; tCK = tCKmin ;
continuous read bursts; IOUT = 0 mA; address inputs are 75
SWITCHING; 50% data change each burst transfer
one bank active; BL = 4; tCK = tCKmin ; continuous write
bursts; address inputs are SWITCHING; 50% data change 55
each burst transfer
tRC = tRFCmin ; tCK = tCKmin ; burst refresh; CKE is
HIGH; address and control inputs are SWITCHING; data 50
bus inputs are STABLE
Address and control inputs are STABLE; data bus inputs
are STABLE
10
- 6 - 75 UNIT
38
35 mA
0.3
0.3
mA
0.4
0.4
0.3
0.3
mA
0.4
0.4
10
10 mA
3
3
mA
3
3
mA
3
3
mA
20
20 mA
12
12 mA
70
70 mA
50
50 mA
50
50 mA
10
10
uA
- 48 -
Publication Release Date : Oct, 15, 2012
Revision : A01-004