W948D6FBHX5E-TR Datasheet, PDF (12/60 Pages) Winbond – 256Mb Mobile LPDDR

W948D6FB / W948D2FB
6.1.2 Initialization Waveform Sequence
VDD
256Mb Mobile LPDDR
VDDQ
CK
CK
200us
tCK
tRP
tRFC
tRFC
tMRD
tMRD
CKE
Command
NOP
PRE
ARF
ARF
MRS
MRS
ACT
Address
A10
BA0,BA1
DM
DQ,DQS
(High-Z)
All
Banks
CODE
CODE
RA
CODE
CODE
RA
BA
BA0=L
BA1=L
BA0=L
BA1=H
VDD/VDDQ powered up
Clock stable
Load
Mode Reg.
Load
Ext.Mode Reg..
= Don't Care
6.2 Register Definition
6.2.1 Mode Register Set Operation
The Mode Register is used to define the specific mode of operation of the LPDDR SDRAM. This definition includes
the definition of a burst length, a burst type, a CAS latency as shown in the following figure.
The Mode Register is programmed via the MODE REGISTER SET command (with BA0=0 and BA1=0) and will
retain the stored information until it is reprogrammed, the device goes into Deep Power Down mode, or the device
loses power.
Mode Register bits A0-A2 specify the burst length, A3 the type of burst (sequential or interleave), A4-A6 the CAS
latency. A logic 0 should be programmed to all the undefined addresses bits to ensure future compatibility.
The Mode Register must be loaded when all banks are idle and no bursts are in progress, and the controller must
wait the specified time tMRD before initiating any subsequent operation. Violating either of these requirements will
result in unspecified operation.
Reserved states should not be used, as unknown operation or incompatibility with future versions may result.
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Publication Release Date : Oct, 15, 2012
Revision : A01-004