W948D6FBHX5E-TR Datasheet, PDF (16/60 Pages) Winbond – 256Mb Mobile LPDDR

6.6.1 Extended Mode Register Definition
W948D6FB / W948D2FB
256Mb Mobile LPDDR
BA1 BA0
An....A8 (1)
A7 ~ A5 A4 A3 A2 A1 A0 Address Bus
1
0
0 ( 2)
DS
Reserved
PASR
Extended Mode Reg.
A7 A6 A5
Drive Strength
0
0
0 Full Strength Driver
0
0
1 Half Strength Drive
0
1
0 Quarter Strength Driver
0
1
1 Octant Strength Driver
1
0
0 Three-Quarters Strength Driver
A2 A1 A0
PASR
0
0
0
All banks
0
0
1
1/2 array (BA1=0)
0
1
0
1/4 array (BA1=BA0=0)
0
1
1
Reserved
1
0
0
Reserved
1
0
1
Reserved
1
1
0
Reserved
NOTES:
1
1
1
1.MSB depends on mobile DDR SDRAM density.
2.A logic 0 should be programmed to all unused / undefined bits to ensure future compatibility.
Reserved
6.7 Status Register Read
Status Register Read (SRR) is an optional feature in JEDEC, and it is implemented in this device. With SRR, a
method is defined to read registers from the device. The encoding for an SRR command is the same as a MRS with
BA[1:0]=”01”. The address pins (A[n:0]) encode which register is to be read. Currently only one register is defined at
A[n:0]=0. The sequence to perform an SRR command is as follows:
 All reads/writes must be completed
 All banks must be closed
 MRS with BA=01 is issued (SRR)
 Wait tSRR
 Read issued to any bank/page
 CAS latency cycles later the device returns the registers data as it would a normal read
 The next command to the device can be issued tSRC after the Read command was issued.
The burst length for the SRR read is always fixed to length 2.
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Publication Release Date : Oct, 15, 2012
Revision : A01-004