W948D6FBHX5E-TR Datasheet, PDF (34/60 Pages) Winbond – 256Mb Mobile LPDDR

W948D6FB / W948D2FB
7.6.1 Write Command
CK
CK
CKE
CS
(High)
RAS
CAS
WE
A0-An
A10
BA0,BA1
CA
Enable AP
AP
Disable AP
BA
= Don't Care
BA=BANK Address
CA=Coulmn Address
AP=Auto Precharge
256Mb Mobile LPDDR
7.6.2 Basic Write Timing Parameters
Basic Write timing parameters for DQs are shown in figure below; they apply to all Write operations.
Input data appearing on the data bus, is written to the memory array subject to the DM input logic level appearing
coincident with the data. If a given DM signal is registered Low, the corresponding data will be written to the memory;
if the DM signal is registered High, the corresponding data inputs will be ignored, and a write will not be executed to
that byte / column location.
CK
CK
Case 1:
tDQSS =
min
DQS
DQ, DM
Case 2:
tDQSS =
max
DQS
DQ, DM
t_CK
t_CH
t_CL
t_DQSS
t_DQSH
t_DSH
t_WPRES
t_{WPRE tDH}
t_DS
DI
n
t_DQSS
t_DQSL
t_DQSH
t_WPRES
t_WPRE
t_DS ^tDH
DI
n
t_DSH
t_WPST
t_DSS
t_DQSL
t_DSS
t_WPST
= Don't Care
1) DI n=Data In for column n
2) 3 subsequent elements of Data In are applied in the programmed order following DI n.
3) tDQSS: each rising edge of DQS must fall within the +/-25% window of the corresponding positive
clock edge.
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Publication Release Date : Oct, 15, 2012
Revision : A01-004