TX4939 Datasheet, PDF (754/756 Pages) Toshiba Semiconductor – 64-Bit TX System RISC

General Directions for Using the CRYPT Engine
Toshiba RISC Processor
TX4939
A.6.4.3. Allowable Settings for Simultaneous Processing
The algorithm cannot be switched during the processing of chained descriptors. As for the IbyteCount and ObyteCount
fields, there exist common restrictions on the block size regardless of whether hash padding is performed by hardware or
software. When message padding is performed by software, the processing cannot be completed using descriptors shown
below. It is completed by performing hashing on the padded message using an intermediate hash value as the initial
value.
(1) Cipher (DES, 3DES or AES) + MD5
Start_packet Last_data End_packet
#desc 1 1
0
0
#desc 2 0
1
1
IbyteCount
64*n
64*n
ObyteCount
64*n
64*n + 16
Algorithm
Cipher+ MD5
Cipher+ MD5
next Descriptor
#desc 2
NULL
(2) Cipher (DES, 3DES or AES) + SHA1
Start_packet Last_data End_packet
#desc 1 1
0
0
#desc 2 0
1
1
IbyteCount
64*n
64*n
ObyteCount
64*n
64*n + 20
Algorithm
Cipher+ SHA1
Cipher+ SHA1
next Descriptor
#desc 2
NULL
A
Rev. 3.3 May 18, 2007
A-10