TX4939 Datasheet, PDF (290/756 Pages) Toshiba Semiconductor – 64-Bit TX System RISC

TMR
Toshiba RISC Processor
TX4939
13.6.5. Interval Timer Mode Register n (TMITMRn)
TMITMR0 (0xF010), TMITMR1 (0xF110), TMITMR2 (0xF210),
TMITMR3 (0xFD10), TMITMR4 (0xFE10), TMITMR5 (0xFF10)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name
RESERVED
Type:
Default
15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
Name TIIE
RESERVED
TZCE
Type: R/W
R/W
Default 0
0
Figure 13-11 Interval Timer Mode Register
Bit Mnemonic
31:16
15 TIIE
Table 13-7 Interval Timer Mode Register
Field Name
Reserved
Interval Timer
Interrupt Enable
Description
Timer Interval Interrupt Enable (Default: 0)
Sets Interval Timer TMCPRA Interrupt Enable/Disable.
R/W
⎯
R/W
0: Disable (mask)
1: Enable
14:1
Reserved
⎯
0
TZCE
Interval Timer
Clear Enable
Interval Timer Zero Clear Enable (Default: 0)
R/W
13
This bit specifies whether or not to clear the counter to “0” after the count
value matches Compare Register A. Count stops at this value if it is not
cleared.
0: Do not clear
1: Clear
Rev. 3.3 May 18, 2007
13-16