TX4939 Datasheet, PDF (559/756 Pages) Toshiba Semiconductor – 64-Bit TX System RISC

EMAC
Toshiba RISC Processor
TX4939
18.4.5. MAC Control, Status Register group
18.4.5.1. MAC Control Register (MAC_Ctl) 0x40
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name
RESERVED
TYPE
Default
Name
15 14
Reserved
13
EnMiss
Roll
12 11
Reserved
10
Miss
Roll
9
8
7
Reserved
6
5
Conn
4
3
2
1
0
Mac
Loop
Full
Dup
Reset
HaltI
mm
Halt
Req
TYPE
R/W
R
Default
0
0
R/W R/W R/W R/W R/W R/W
000000
Bit(s)
31 : 14
13
Mnemonic
EnMissRoll
12:11
10
MissRoll
9:7
6:5
Conn
4
MacLoop
3
FullDup
2
Reset
1
HaltImm
0
HaltReq
Field Name
Reserved
Missing Error Counter
Rollover Enable
Reserved
Missing Error Counter
Rollover
Reserved
Connection Mode
MAC Loop Back
Full Duplex Mode
Software Reset
Immediate Halt
Halt Request
Description
EnMissRoll (Default: 0, R/W)
Issues an interrupt when the count value of the Missing Error Count Register
rolls over from 0x7FFF to 0x8000.
MissRoll (Default: 0, R)
Indicates that the count value of the Missing Error Count Register rolled over
from 0x7FFF to 0x8000. (Read only)
Conn (Default: 00, R/W)
This field selects the connection mode.
00: Automatic (default)
01: Reserved
10: MII (MII clock determines the transfer rate)
11: Reserved
MacLoop (Default: 0, R/W)
Directly provides the transmission signal as the input of the reception circuit
without sending it outside the Ethernet Controller.
FullDup (Default: 0, R/W)
Set this bit to "1" for full duplex.
Reset (Default: 0, R/W)
Resets all State Machines and FIFOs of the Ethernet Controller.
HaltImm (Default: 0, R/W)
Immediately halts transmission or reception when set to “1”.
When receiving data, if this bit is set after MAC starts processing the recipient
address, reception operation for the current packet continues and the data is
transferred to system memory. At this time, if the RxHalted bit of the Reception
Status Register is set, it indicates that the system sent a Reception Halt Request
while a packet was being received.
If this bit is set before starting processing of the recipient address, reception
operation is immediately halted. The RxHalted bit will then be set.
HaltReq (Default: 0, R/W)
Halts transmission/reception when the packet currently in progress ends.
Figure 18-46 MAC Control Register
Hardware resets initialize the MAC Control Register to 0x8000. Setting the Reset bit (bit 2) executes software reset.
Starting software reset clears bit 2. The other bits do not affect software resets.
18
The MAC Control Register is used to display total control and status information of MAC. The MissRoll bit is the status bit.
All other bits are control bits.
After the Reset bit is set, 4 MII transmission or reception clock cycles pass, then software reset is executed for several
cycles. Therefore, after writing to the Reset bit, do not access the Ethernet Controller until 320 ns pass for 100 Mbps
transfer or until 3,200 ns pass for 10 Mbps transfer. Before performing reset, you can use the MAC Transmission Control
Register (Tx_Ctl) or MAC Reception Control Register (Rx_Ctl) to issue a Halt Request to end the current network
transaction.
The MissRoll bit is set when the counter rolls over from 0x7FFF to 0x8000, and is reset when the software reads the
Missing Error Count Register. See 18.4.5.7 Missing Error Count Register for an explanation.
Some PHYs do not support full duplex transfer. The MacLoop bit has higher priority than the FullDup bit.
Rev. 3.3 May 18, 2007
18-61