TX4939 Datasheet, PDF (624/756 Pages) Toshiba Semiconductor – 64-Bit TX System RISC

Toshiba RISC Processor
I2C
TX4939
22.3.4. Data Transfer
22.3.4.1. Byte Mode:
Once successful slave addressing has been achieved, the data transfer can proceed on a byte-by-byte basis in the
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direction specified by the RW bit sent by the master. Each transferred byte is followed by an acknowledge bit on the 9th
SCL clock cycle. If the slave signals a No Acknowledge, the master can generate a STOP signal to abort the data
transfer or generate a Repeated START signal and start a new transfer cycle.
If the master, as the receiving device, does not acknowledge the slave, the slave releases the SDA line for the master to
generate a STOP or Repeated START signal.
To write data to a slave, store the data to be transmitted in the Transmit Register and set the WR bit. To read data from a
slave, set the RD bit. During a transfer the core set the TIP flag, indicating that a Transfer is In Progress. When the
transfer is done the I2C_DSTS (done) flag is reset, the I2C_DSTS done flag set and, when interrupt enabled, an interrupt
generated. The Receive Register contains valid data after the I2C_DSTS flag has been set. The user may issue a new
write or read command when the I2C_DSTS flag is reset.
22.3.5. STOP signal
The master can terminate the communication by generating a STOP signal. A STOP signal, usually referred to as the P-
bit, is defined as a low-to-high transition of SDA while SCL is at logical ‘1’.
22.3.6. Arbitration Procedure
Since the I2C core supports single master configurations only, no Arbitration logic is added to the core. Only clock
synchronization is supported since slave devices can use this protocol for clock stretching.
22.3.7. Clock Synchronization
Since the logical AND function is performed on the I2C signals, a high to low transition on SCL or SDA affects all devices
connected to the bus. The SCL clock signal can be synchronized between multiple masters using this feature. Each
device starts counting its SCL low period when the current master drives SCL low. Once a device’s clock has gone low, it
holds the SCL line low until the clock-high-state is reached.
wait
SCL1
SCL2
SCL
Start counting
low period here
Internal SCL first
Internal SCL secondary
Resulting SCL
Figure 22-3 Clock Synchronization
Rev. 3.3 May 18, 2007
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