TX4939 Datasheet, PDF (638/756 Pages) Toshiba Semiconductor – 64-Bit TX System RISC

I2S
MCLK
SCK
(DIV = 2)
SCK
(DIV = 3)
SCK
(DIV = 4)
Toshiba RISC Processor
TX4939
23
Figure 23-7 MCLK and SCK with Divider Value
23.2.4. MCLK and WS Detection
In I2S controller, there is logic that checks MCLK and WS clock frequency.
For MCLK detection, fast clock (150 MHz) uses to sample the MCLK clock. At every rising edge of MCLK, the counter
begins to count (from “0”) base on 150 MHz clock. And also at every rising edge of MCLK, this count value get compare
with the MCLK check value (register bits). If the count value is greater then MCLK check value, which means MCLK is
out of range, Interrupt will get set. Otherwise it continues sampling MCLK. Once out of range detect, counter logic will
stop counting.
For the WS detection, the logic simply samplings the WS with SCK clock. At every rising and falling edge of WS, counter
starts counting from “0” base on SCK clock. It also compares the counter value at every rising edge of WS. If counter
value match the setting in the control register (time slot – 32, 48, 64) means WS frequency is correct. If counter value
does not match, WS interrupt sets to high and counter logic detection stops counting.
Rev. 3.3 May 18, 2007
23-8