TX4939 Datasheet, PDF (730/756 Pages) Toshiba Semiconductor – 64-Bit TX System RISC

Electrical
Toshiba RISC Processor
TX4939
28.4.4. External Bus Interface AC Characteristics
(Tc = 0 - 85°C, VDD33 = 3.3 V ± 0.2 V, VDD25 = 2.5 V ± 0.2 V, VDDC = 1.25 V ± 0.062 V, VSS = 0 V)
Item
Symbol
Condition
Min. Max.
SYSCLK Cycle Time
SYSCLK High Time
SYSCLK Low Time
SA[5:0] Output Delay
CE[7:0]* Output Delay
OE* Output Delay
SWE* Output Delay
BWE[1:0]* Output Delay
ACE Output Delay
SADB[15:0] Output Delay (H→L, L→H)
SADB[15:0] Output Delay (Hi-Z→Valid)
DATA[15:0] Ouput Delay (Valid→Hi-Z)
SADB[15:0] Input Setup Time
SADB[15:0] Input Hold Time
ACK* Output Delay (H→L, L→H)
ACK* Input Setup Time
ACK* Input Hold Time
t_{CYC_SYSCLK}
t_{HIGH_SYSCLK}
t_{LOW_SYSCLK}
t_{VAL_ADDR2}
t_{VAL_CE}
t_{VAL_OE}
t_{VAL_SWE}
t_{VAL_BWE}
t_{VAL_ACE}
t_{VAL_BUS}
t_{VAL_DATA2ZV}
t_{VAL_DATA2VZ}
t_{SU_DATA2}
t_{HO_DATA2}
t_{VAL_ACK}
t_{SU_ACK}
t_{HO_ACK}
Buffer fixed: CL=50 pF, 4 mA
Buffer fixed: CL=50 pF, 4 mA
Buffer fixed: CL=50 pF, 4 mA
For CL=50 pF, 4 mA buffer
Buffer fixed: CL=50 pF, 4 mA
Buffer fixed: CL=50 pF, 4 mA
Buffer fixed: CL=50 pF, 4 mA
Buffer fixed: CL=50 pF, 4 mA
Buffer fixed: CL=50 pF, 4 mA
For CL=50 pF, 4 mA buffer
For CL=50 pF, 4 mA buffer
For CL=50 pF, 4 mA buffer
Buffer fixed: CL=50 pF, 4 mA
10
⎯
4
⎯
4
⎯
1.5
8.5
1.5
8.5
1.5
8.5
1.5
8.5
1.5
8.5
1.5
8.5
1.5 8.5 (1)
1.5
8.5
-1
8.5
6.0
⎯
0.5
⎯
1.5
8.5
6.0
⎯
0.5
⎯
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Note 1:
When the speed of the Local Bus is set to 1/3,1/4,1/5, 1/6 speed, write data delay has 10 ns more for
synchronization
28
SYSCLK
OUTPUT
INPUT
External Bus Interface Timing Diagram
t_{HIGH_SYSCLK}
t_{LOW_SYSCLK}
t_{VAL_**}
t_{CYC_SYSCLK}
outputs valid
t_{SU_**}
t_{HO_**}
inputs valid
Figure 28-10 External Bus Interface Timing Diagram
Rev. 3.3 May 18, 2007
28-10