TX4939 Datasheet, PDF (223/756 Pages) Toshiba Semiconductor – 64-Bit TX System RISC

EBC
Toshiba RISC Processor
TX4939
9.4.7. External ACK Mode Access (16-bit Bus)
1-Half-Word Single Write (0 Wait, SHWT=0, External ACK*, 16-bit Bus)
0 S11 E2S1 E3S2 E4S3 S52 S63 7
8
9
10 11 12 13 14 15 16 17 18 19
SYSCLK
CE*
SA [5:0]
AD [21:6]
ACE*
OE*
SWE*
BWE*
F
0
F
F
BE* F
0
F
SADB [15:0]
ACK*/READY
INPUT
9
Rev 2.12
Note 1:
Note 2:
Note 3:
The TX4939 sets the ACK* signal to High Impedance in the S1 State.
External devices drive the ACK* signal to Low (assert the signal) until the ES1 State.
External devices drive the ACK* signal to High (deassert the signal) in the ES2 State. If an external
device is late in asserting ACK*, then the Wait State is inserted for the amount of time the external
device is late. If a certain condition is met, it is okay for the ACK* signal to be driven to Low for 1 clock
cycle or more. See 9.2.8.4 ACK* Input Timing (External ACK Mode) for more information.
Figure 9-30 1-half-word Single Write (0 Wait, SHWT=0, External ACK*, 16-bit Bus)
1-Half-Word Single Read (0 Wait, SHWT=0, External ACK*, 16-bit Bus)
0 S11 E2S1 E3S2 S42 S53 6
7
8
9
10 11 12 13 14 15 16 17 18 19
SYSCLK
CE*
SA [5:0]
AD [21:6]
ACE*
OE*
SWE*
BWE*
F
F
BE* F
0
F
F
SADB [15:0]
ACK*/READY
INPUT
Figure 9-31 1-half-word Single Read (0 Wait, SHWT=0, External ACK*, 16-bit Bus)
Rev 2.12
Rev. 3.3 May 18, 2007
9-27