TX4939 Datasheet, PDF (26/756 Pages) Toshiba Semiconductor – 64-Bit TX System RISC

Toshiba RISC Processor
Index
TX4939
Table 16-29 PCI Status Interrupt Mask Register................................................................................................. 16-40
Table 16-30 P2G Configuration Register ............................................................................................................ 16-41
Table 16-31 P2G Status Register ....................................................................................................................... 16-42
Table 16-32 P2G Interrupt Mask Register .......................................................................................................... 16-43
Table 16-33 P2G Current Command Register .................................................................................................... 16-43
Table 16-34 PCI Bus Arbiter Request Port Register ........................................................................................... 16-44
Table 16-35 PCI Bus Arbiter Configuration Register........................................................................................... 16-46
Table 16-36 PCI Bus Arbiter Status Register ...................................................................................................... 16-47
Table 16-37 PCI Bus Arbiter Interrupt Mask Register ......................................................................................... 16-47
Table 16-38 PCI Bus Arbiter Broken Master Register......................................................................................... 16-48
Table 16-39 PCI Bus Arbiter Current Request Register...................................................................................... 16-49
Table 16-40 PCI Bus Arbiter Current Grant Register .......................................................................................... 16-49
Table 16-41 PCI Bus Arbiter Current State Registe ............................................................................................ 16-50
Table 16-42 G2P Memory Space 0 G-Bus Base Address Register .................................................................... 16-51
Table 16-43 G2P Memory Space 1 G-Bus Base Address Register .................................................................... 16-52
Table 16-44 G2P Memory Space 2 G-Bus Base Address Register .................................................................... 16-53
Table 16-45 G2P I/O Space G-Bus Address Register......................................................................................... 16-54
Table 16-46 G2P Memory Space 0 Address Mask Register ............................................................................... 16-55
Table 16-47 G2P Memory Space 1 Address Mask Register ............................................................................... 16-55
Table 16-48 G2P Memory Space 2 Address Mask Register ............................................................................... 16-56
Table 16-49 G2P I/O Space Address Mask Register .......................................................................................... 16-56
Table 16-50 G2P Memory Space 0 G-Bus Base Address Register .................................................................... 16-57
Table 16-51 G2P Memory Space 1 G-Bus Base Address Register .................................................................... 16-58
Table 16-52 G2P Memory Space 2 G-Bus Base Address Register .................................................................... 16-59
Table 16-53 G2P I/O Space G-Bus Address Register......................................................................................... 16-60
Table 16-54 PCI Controller Configuration Register............................................................................................. 16-61
Table 16-55 PCI Controller Status Register ........................................................................................................ 16-64
Table 16-56 PCI Controller Interrupt Mask Register ........................................................................................... 16-66
Table 16-57 P2G Memory Space 0 G-Bus Base Address Register .................................................................... 16-67
Table 16-58 P2G Memory Space 1 G-Bus Base Address Register .................................................................... 16-68
Table 16-59 P2G Memory Space 2 G-Bus Base Address Register .................................................................... 16-69
Table 16-60 P2G I/O Space G-Bus Base Address Register................................................................................ 16-70
Table 16-61 G2P Configuration Address Register .............................................................................................. 16-71
Table 16-62 PCI Configuration Space Access Address ...................................................................................... 16-72
Table 16-63 G2P Configuration Data Register.................................................................................................... 16-72
Table 16-64 G2P Interrupt Acknowledge Data Register...................................................................................... 16-73
Table 16-65 G2P Special Cycle Data Register ................................................................................................... 16-73
Table 16-66 ID Register ...................................................................................................................................... 16-74
Table 16-67 Class Code/Revision ID Register.................................................................................................... 16-74
Table 16-68 Sub System ID Register.................................................................................................................. 16-75
Table 16-69 PCI Configuration Register 2 .......................................................................................................... 16-75
Table 16-70 PDMAC Chain Address Register .................................................................................................... 16-76
Table 16-71 G-Bus Address Register ................................................................................................................. 16-77
Table 16-72 PCI Bus Address Register .............................................................................................................. 16-78
Table 16-73 Count Register ................................................................................................................................ 16-79
Table 16-74 PDMAC Control Register ................................................................................................................ 16-80
Table 16-75 Status Register................................................................................................................................ 16-82
Table 16-76 PCI Configuration Space Register .................................................................................................. 16-85
Table 16-77 Memory Space (m) Lower Base Address Register.......................................................................... 16-86
Table 16-78 Correspondence of BA [28:20] field ................................................................................................ 16-86
Table 16-79 IO Space Base Address Register.................................................................................................... 16-87
Table 16-80 Capability ID Register ..................................................................................................................... 16-87
Table 16-81 Next Item Pointer Register .............................................................................................................. 16-87
Table 16-82 PMC Register.................................................................................................................................. 16-88
Table 16-83 PMCSR Register............................................................................................................................. 16-89
Table 17-1 System Control Register ..................................................................................................................... 17-8
Table 17-2 Additional Control Register ............................................................................................................... 17-13
Table 17-3 PIO Access Address Register ........................................................................................................... 17-17
Table 17-4 Interrupt Control Register.................................................................................................................. 17-19
Table 17-5 Timing Error Threshold ..................................................................................................................... 17-20
Table 17-6 ATAPI Packet Command Register .................................................................................................... 17-21
Table 17-7 ATA Device Timing Error Register ..................................................................................................... 17-22
Table 17-8 Packet Transfer Control Register ...................................................................................................... 17-23
Table 17-9 PIO Transfer Timing .......................................................................................................................... 17-26
Table 17-10 Multiword DMA Transfer Timing ...................................................................................................... 17-28
Table 17-11 Timing Parameters when Ultra DMA Transfer Starts ....................................................................... 17-30
Rev. 3.3 May 18, 2007
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