TX4939 Datasheet, PDF (233/756 Pages) Toshiba Semiconductor – 64-Bit TX System RISC

NDFMC
Toshiba RISC Processor
TX4939
10.3. Detailed Operation
10.3.1. Registers
Offset Address
0x5000
0x5008
0x5010
0x5018
0x5020
0x5028
Bit Width
32
32
32
32
32
32
Table 10-1 NDFMC Registers
Register Symbol
NDFDTR
NDFMCR
NDFSR
NDFISR
NDFIMR
NDFSPR
Register Name
NAND Flash Memory Data Transfer Register (R/W)
NAND Flash Memory Mode Control Register (R/W)
NAND Flash Memory Status Register (Read)
NAND Flash Memory Controller Reset (Write)
NAND Flash Memory Interrupt Status Register(RO)
NAND Flash Memory Interrupt Mask Register (R/W)
NAND Flash Memory Strobe Pulse Width Register(R/W)
10.3.2. Convention for following explanation
NDFDTR and NDFMCR are the essential registers. Figure 10-2 shows field definition of them.
NDFDTR
15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
DATA [15:8]
DATA [7:0]
NDFMCR
10
15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
X16 DMAREQ WE
ECC
CE
CS[1:0] ALE CLE
Figure 10-2 Field Definition of Registers NDFDTR and NDFMCR
Table 10-2 and Table 10-3 show Mnemonics used in this section. In addition, following expressions mean writing the
parameter in to corresponding register.
$NDFMCR = CLE | CE ; // Write 0x0011 to register NDFMCR
Mnemonic
NDC_READ1
NDC_READ2
NDC_READ3
NDC_WRITE
NDC_AUTOP
NDC_STATS
NDC_READID
NDC_RESET
Mnemonic
ND_CLE
ND_ALE
ND_CH0
ND_CH1
ND_CH2
ND_CH3
ND_CE
ND_ECCR
ND_ECCE
ND_ECCD
ND_ECCRD
ND_WE
ND_DMA1
ND_DMA2
ND_DMA3
ND_X16B
Table 10-2 Mnemonic Command Parameter for NDFDTR
Value
0x00
0x01
0x50
0x80
0x10
0x70
0x90
0xFF
Explanation
NAND Flash Command READ Data from 0 to 255 byte position
NAND Flash Command READ Data from 256 to 511 byte position.
NAND Flash Command READ Data from the redundant byte
NAND Flash Command WRITE Data from the top of page.
NAND Flash Command Invoke Auto-Program Operation
NAND Flash Command READ Status
NAND Flash Command ID READ operation
NAND Flash Command Initialize NAND
Value
0x0001
0x0002
0x0000
0x0004
0x0008
0x000C
0x0010
0x0060
0x0020
0x0000
0x0040
0x0080
0x0100
0x0200
0x0300
0x0400
Table 10-3 Mnemonic Parameter for NDFMCR
Explanation
Assert CLE
Assert ALE
Select NAND #0
Select NAND #2
Select NAND #3
Select NAND #4
Activate NAND Controller
Reset ECC Circuit
ECC Enable
ECC Disable
READ ECC generated by NDFMC or UPDATE external latch
Activate Write Enable
Activate 128 Byte DMA Transfer
Activate 256 Byte DMA Transfer
Activate 512 Byte DMA Transfer
Set to 16-bit Bus Mode
Rev. 3.3 May 18, 2007
10-3