TX4939 Datasheet, PDF (149/756 Pages) Toshiba Semiconductor – 64-Bit TX System RISC

Configuration
Toshiba RISC Processor
TX4939
Bit
19:17
Table 7-2 Chip Configuration Register
Mnemonic
MULCLK
Field Name
CPUCLK
Frequency
Multiplication
Factor
Description
Initial Value R/W
Indicates information about the frequency multiplication
SA[2:0]
R/O
factor of the TX49/H4 core clock (CPUCLK) to the
MSTCLK. This field is set with a result of encoding an initial
input value at SA[2:0].
The PLL incorporated in the TX4939 multiplies the
MSTCLK and supplies the resulting frequency to the
TX49/H4 core.
The value set in YMULCLK [4:0] is reflected in the EC field
of the TX49/H4 core Configuration register.
MULCLK[2:0] ==> YMULCLK[4:0] = ND[4:0]
MULCLK[2:0] ND[4:0]
PLL#2
CPU Clock
000
5'b01000 600 MHz 300 MHz
001
5'b 01001 666 MHz 333 MHz
010
5'b 01010 733 MHz 366 MHz
011
5'b 01011 800 MHz 400 MHz
100
5'b 01100 Reserved Reserved
7
101
5'b 01101 Reserved Reserved
110
5'b 01110 Reserved Reserved
111
5'b 00111 533 MHz 266 MHz
16
15
14
13
12:10
9
8
7:6
5
BEOW
WR
TOE
PCIARB
YDIVMODE
PTSEL
BESEL
SYSSP
ACKSEL
Write-Access
Bus Error
Watchdog
Timer Mode
G-Bus
Timeout Error
Detection
PCI Arbiter
Selection
GBUSCLK
Frequency
Division Ratio
PC Trace
Mode
BE function
SYSCLK
frequency
division ratio
Boot ACK* I/P
The following equation defines the CPUCLK frequency as a
function of the MSTCLK frequency and YMULCLK:
CPUCLK(f) = (25 x YMULCLK x MSTCLK(f) ) / 36
Indicates that a timeout error has occurred in the internal 0
bus (G-Bus) during a write bus transaction of the TX49/H4
core. This bit corresponds to interrupt No. 2 in the interrupt
controller.
0 = No error has occurred.
1 = An error has occurred.
Specifies how information will be reported in watchdog
0
timer mode.
0 = Generate an NMI exception.
1 = Generate a watchdog reset.
Specifies whether to detect and report a bus timeout error in 0
the internal bus (G-Bus) of the TX4939.
0 = Do not detect or report a bus timeout error.
1 = Detect and report a bus timeout error.
Indicates the PCI bus arbiter selection setting
SADB[6]
0 = Select external PCI bus arbiter
1 = Select built-in PCI bus arbiter
Specifies the frequency division ratio of the GBUS clock
output (GBUSCLK) frequency to the clock frequency
(CPUCLK) of the TX49/H4 core.
000:GBUSCLK frequency = CPUCLK frequency ÷ 2
001:GBUSCLK frequency = CPUCLK frequency ÷ 3
110:GBUSCLK frequency = CPUCLK frequency ÷ 5
111:GBUSCLK frequency = CPUCLK frequency ÷ 6
PC Trace Mode Enable
0 = PC Trace Disable
1 = PC Trace Enable
Specifies the function of BE[1:0]*/BWE[1:0]* pins upon
booting
0: BE[1:0]* (Byte Enable)
1: BWE[1:0]* (Byte Write Enable)
Indicates the frequency division ratio of the SYSCLK
frequency to the G-Bus clock frequency (GBUSCLK).
00: SYSCLK frequency = GBUSCLK frequency ÷ 4
01: SYSCLK frequency = GBUSCLK frequency ÷ 3
10: SYSCLK frequency = GBUSCLK frequency ÷ 5
11: SYSCLK frequency = GBUSCLK frequency ÷ 6
Specifies the access mode for external bus controller
channel0
0 = External ACK mode
1 = Normal mode
{
DMAACK[1],
DMAACK[1:0]
}
SADB[0]
SADB[1]
SA[4:3]
SADB[2]
RW1C
R/W
R/W
R/O
R/O
R/W
R/O
R/O
R/O
Rev. 3.3 May 18, 2007
7-5