TX4939 Datasheet, PDF (200/756 Pages) Toshiba Semiconductor – 64-Bit TX System RISC

EBC
Toshiba RISC Processor
TX4939
9.2.4. External Address Output
SA [5:0] is dedicated address signal. The middle address will be provided through SADB [15:0].
External device latches the middle sixteen address bits and the upper six address bits by using the ACE* signal. Either the
ACE* signal itself can be used as a Latch Enable signal or the upper and middle address can be latched at the rise of
SYSCLK when the ACE* signal is being asserted.
The ADDR signal output is held for one clock cycle after the ACE* signal rise when the CCFG.ACEHOLD bit is set (default).
The ADDR signal output is not held when the CCFG.ACEHOLD bit is cleared. This hold time setting is applied globally to all
channels.
The ACE* signal of the upper address is always asserted for starting of every transaction. When there is a burst transfer,
ACE* signal is only asserted for the first cycle.
9.2.5. Address Bit Corresponding in the 16-bit Mode
In case of 16-bit data bus width mode, 512 MB memory space (2²⁹) is accessible. Table 9-4 shows this corresponding.
Table 9-4 Address Bit Correspondin in the 16-bit Mode
9
Latched SADB Bit
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Middle Address
22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7
Latched SA Bit
Upper Address
543210
Non-latched SA
54 3 2 10
28 27 26 25 24 23
Lower Address
65 4 3 21
Note: Address is expressed by BYTE ADDRESS
When a Single cycle that accesses 1-Byte or 1 half-word data is executed, 16-bit access is executed only once on the
external bus. 16-bit access is executed twice when performing 1-word access. 16-bit access is executed four times when
performing 1-double-word access. When a Burst cycle is executed, four 16-bit cycles are executed for each Burst access
when the Bus cycle tries to request a byte combination other than double-word data.
9.2.6. Address Bit Corresponding in the 8-bit Mode
In case of 8-bit data bus width mode, 256 MB memory space (2²⁸) is accessible. Table 9-5 shows this corresponding.
Latched SADB
Middle Address
Table 9-5 Address Bit Correspondin in the 8-bit Mode
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6
Latched SA
Upper Address
543210
Non-latched SA
54 3 2 10
27 26 25 24 23 22
Lower Address
54 3 2 10
Note: Address is expressed by BYTE ADDRESS
When a Single cycle that accesses 1-Byte data is executed, 8-bit access is executed only once on the external bus. 8-bit
access is executed twice when performing 1-half-word access. 8-bit access is executed four times when performing 1-word
access. 8-bit access is executed eight times when performing 1-double-word access. When a Burst cycle is executed, eight
8-bit cycles are executed for each Burst access when the Bus cycle tries to request a byte combination other than
double-word data.
Rev. 3.3 May 18, 2007
9-4