AM1707_14 Datasheet, PDF (93/201 Pages) Texas Instruments – Microprocessor

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AM1707
SPRS637E – FEBRUARY 2010 – REVISED JUNE 2014
HEX ADDRESS RANGE
0x01E2 0000 - 0x01E2 1FFF
Table 6-37. EMAC Control Module RAM
EMAC Local Buffer Descriptor Memory
Table 6-38. RMII Timing Requirements
No.
1 tc(REFCLK)
PARAMETER
Cycle Time, RMII_MHZ_50_CLK⁽¹⁾
MIN TYP MAX UNIT
20
ns
2 tw(REFCLKH)
Pulse Width, RMII_MHZ_50_CLK High
7
13 ns
3 tw(REFCLKL)
Pulse Width, RMII_MHZ_50_CLK Low
7
13 ns
6 tsu(RXD-REFCLK)
Input Setup Time, RXD Valid before RMII_MHZ_50_CLK High
4
ns
7 th(REFCLK-RXD)
Input Hold Time, RXD Valid after RMII_MHZ_50_CLK High
2
ns
8 tsu(CRSDV-REFCLK)
Input Setup Time, CRSDV Valid before RMII_MHZ_50_CLK High
4
ns
9 th(REFCLK-CRSDV)
Input Hold Time, CRSDV Valid after RMII_MHZ_50_CLK High
2
ns
10 tsu(RXER-REFCLK)
Input Setup Time, RXER Valid before RMII_MHZ_50_CLK High
4
ns
11 th(REFCLKR-RXER)
Input Hold Time, RXER Valid after RMII_MHZ_50_CLK High
2
ns
(1) Per the RMII industry specification, the RMII reference clock (RMII_MHZ_50_CLK) must have jitter tolerance of 50 ppm or less.
No.
4 td(REFCLK-TXD)
5 td(REFCLK-TXEN)
Table 6-39. RMII Switching Characteristics
PARAMETER
Output Delay Time, RMII_MHZ_50_CLK High to TXD Valid
Output Delay Time, RMII_MHZ_50_CLK High to TXEN Valid
MIN TYP MAX UNIT
2.5
13 ns
2.5
13 ns
1
RMII_MHz_50_CLK
23
5
RMII_TXEN
RMII_TXD[1:0]
RMII_RXD[1:0]
RMII_CRS_DV
RMII_RXER
4
8
5
6
7
9
10
11
Figure 6-30. RMII Timing Diagram
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Peripheral Information and Electrical Specifications
93
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