AM1707_14 Datasheet, PDF (80/201 Pages) Texas Instruments – Microprocessor

AM1707
SPRS637E – FEBRUARY 2010 – REVISED JUNE 2014
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6.11.4 EMIFB Electrical Data/Timing
Table 6-26. EMIFB SDRAM Interface Timing Requirements
NO.
CVDD = 1.3 V⁽¹⁾
MIN
MAX
CVDD = 1.2V⁽²⁾ _UNI
MIN
MAX ^T
19 t_(DV-CLKH)
Input setup time, read data valid on EMB_D[31:0] before
EMB_CLK rising
0.59
0.8
ns
20 t_h(CLKH-DIV)
Input hold time, read data valid on EMB_D[31:0] after
EMB_CLK rising
1.25
1.5
ns
(1) Commercial (default), Industrial and Extended temperature range rated devices for 456 MHz max CPU operating frequency as
applicable to the device
(2) Commercial (default), Industrial, Extended and Automotive temperature range rated devices for 400/375/300/266/200 MHz max CPU
operating frequencies as applicable to the device
Table 6-27. EMIFB SDRAM Interface Switching Characteristics for Commercial (Default) Temperature
Range
NO.
PARAMETER
CVDD = 1.3 V⁽¹⁾
MIN
MAX
CVDD = 1.2V⁽²⁾ _UNI
MIN
MAX ^T
1 t_c(CLK)
Cycle time, EMIF clock EMB_CLK
6.579
7.5
ns
2 t_w(CLK)
Pulse width, EMIF clock EMB_CLK high or low
2.63
3
ns
3 t_d(CLKH-CSV)
Delay time, EMB_CLK rising to EMB_CS[0] valid
4.25
5.1 ns
4 t_{oh(CLKH-CSIV)}
Output hold time, EMB_CLK rising to EMB_CS[0] invalid
1.1
1.1
ns
5 t_d(CLKH-DQMV)
Delay time, EMB_CLK rising to EMB_WE_DQM[3:0] valid
4.25
5.1 ns
6 t_{oh(CLKH-DQMIV)}
Output hold time, EMB_CLK rising to EMB_WE_DQM[3:0]
invalid
1.1
1.1
ns
7 t_d(CLKH-AV)
Delay time, EMB_CLK rising to EMB_A[12:0] and
EMB_BA[1:0] valid
4.25
5.1 ns
8 t_oh(CLKH-AIV)
Output hold time, EMB_CLK rising to EMB_A[12:0] and
EMB_BA[1:0] invalid
1.1
1.1
ns
9 t_d(CLKH-DV)
10 t_oh(CLKH-DIV)
11 t_d(CLKH-RASV)
12 t_{oh(CLKH-RASIV)}
13 t_d(CLKH-CASV)
14 t_{oh(CLKH-CASIV)}
15 t_d(CLKH-WEV)
16 t_{oh(CLKH-WEIV)}
17 t_{dis(CLKH-DHZ)}
18 t_(CLKH-DLZ)
Delay time, EMB_CLK rising to EMB_D[31:0] valid
Output hold time, EMB_CLK rising to EMB_D[31:0] invalid
Delay time, EMB_CLK rising to EMB_RAS valid
Output hold time, EMB_CLK rising to EMB_RAS invalid
Delay time, EMB_CLK rising to EMB_CAS valid
Output hold time, EMB_CLK rising to EMB_CAS invalid
Delay time, EMB_CLK rising to EMB_WE valid
Output hold time, EMB_CLK rising to EMB_WE invalid
Delay time, EMB_CLK rising to EMB_D[31:0] tri-stated
Output hold time, EMB_CLK rising to EMB_D[31:0] driving
4.25
5.1 ns
1.1
1.1
ns
4.25
5.1 ns
1.1
1.1
ns
4.25
5.1 ns
1.1
1.1
ns
4.25
5.1 ns
1.1
1.1
ns
4.25
5.1 ns
1.1
1.1
ns
(1) Commercial (default) temperature range rated devices for 456 MHz max CPU operating frequency as applicable to the device
(2) Commercial (default) temperature range rated devices for 400/375/300/266/200 MHz max CPU operating frequencies as applicable to
the device
Table 6-28. EMIFB SDRAM Interface Switching Characteristics for Industrial, Extended, and Automotive
Temperature Ranges
NO.
PARAMETER
CVDD = 1.3 V⁽¹⁾
MIN
MAX
CVDD = 1.2V⁽²⁾ _UNI
MIN
MAX ^T
1 t_c(CLK)
2 t_w(CLK)
3 t_d(CLKH-CSV)
4 t_{oh(CLKH-CSIV)}
Cycle time, EMIF clock EMB_CLK
Pulse width, EMIF clock EMB_CLK high or low
Delay time, EMB_CLK rising to EMB_CS[0] valid
Output hold time, EMB_CLK rising to EMB_CS[0] invalid
6.579
7.5
ns
2.63
3
ns
4.25
5.1 ns
1.1
0.9
ns
(1) Industrial temperature range rated devices for 456 MHz max CPU operating frequency as applicable to the device
(2) Industrial, Extended and Automotive temperature range rated devices for 400/375/300/266/200 MHz max CPU operating frequencies as
applicable to the device
80
Peripheral Information and Electrical Specifications
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