AM1707_14 Datasheet, PDF (118/201 Pages) Texas Instruments – Microprocessor

AM1707
SPRS637E – FEBRUARY 2010 – REVISED JUNE 2014
www.ti.com
Table 6-62. General Timing Requirements for SPI1 Master Modes⁽¹⁾ (continued)
No.
6
t_{oh(SPC_SIMO)M}
7
t_{su(SOMI_SPC)M}
8
t_{ih(SPC_SOMI)M}
PARAMETER
Polarity = 0, Phase = 0,
from SPI1_CLK falling
Output hold time, SPI1_SIMO
valid after
receive edge of SPI1_CLK
Polarity = 0, Phase = 1,
from SPI1_CLK rising
Polarity = 1, Phase = 0,
from SPI1_CLK rising
Polarity = 1, Phase = 1,
from SPI1_CLK falling
Polarity = 0, Phase = 0,
to SPI1_CLK falling
Input Setup Time, SPI1_SOMI
valid before receive edge of
SPI1_CLK
Polarity = 0, Phase = 1,
to SPI1_CLK rising
Polarity = 1, Phase = 0,
to SPI1_CLK rising
Polarity = 1, Phase = 1,
to SPI1_CLK falling
Polarity = 0, Phase = 0,
from SPI1_CLK falling
Input Hold Time, SPI1_SOMI
valid after receive edge of
SPI1_CLK
Polarity = 0, Phase = 1,
from SPI1_CLK rising
Polarity = 1, Phase = 0,
from SPI1_CLK rising
Polarity = 1, Phase = 1,
from SPI1_CLK falling
MIN
0.5t_c(SPC)M - 3
0.5t_c(SPC)M - 3
0.5t_c(SPC)M - 3
0.5t_c(SPC)M - 3
0
0
0
0
5
5
5
5
MAX
UNIT
ns
ns
ns
No.
9
t_c(SPC)S
10 t_w(SPCH)S
11 t_w(SPCL)S
12 t_{su(SOMI_SPC)S}
13 t_{d(SPC_SOMI)S}
Table 6-63. General Timing Requirements for SPI1 Slave Modes⁽¹⁾
PARAMETER
Cycle Time, SPI1_CLK, All Slave Modes
Pulse Width High, SPI1_CLK, All Slave Modes
Pulse Width Low, SPI1_CLK, All Slave Modes
Polarity = 0, Phase = 0,
to SPI1_CLK rising
Setup time, transmit data written to
SPI before initial clock edge from
master.^{(2) (3)}
Polarity = 0, Phase = 1,
to SPI1_CLK rising
Polarity = 1, Phase = 0,
to SPI1_CLK falling
Polarity = 1, Phase = 1,
to SPI1_CLK falling
Polarity = 0, Phase = 0,
from SPI1_CLK rising
Delay, subsequent bits valid on
SPI1_SOMI after transmit edge of
SPI1_CLK
Polarity = 0, Phase = 1,
from SPI1_CLK falling
Polarity = 1, Phase = 0,
from SPI1_CLK falling
Polarity = 1, Phase = 1,
from SPI1_CLK rising
MIN
greater of 3P or 40
18
18
2P
2P
2P
2P
MAX
UNIT
ns
ns
ns
ns
19
19
ns
19
19
(1) P = SYSCLK2 period
(2) First bit may be MSB or LSB depending upon SPI configuration. SO(0) refers to first bit and SO(n) refers to last bit output on
SPI1_SOMI. SI(0) refers to the first bit input and SI(n) refers to the last bit input on SPI1_SIMO.
(3) Measured from the termination of the write of new data to the SPI module, In analyzing throughput requirements, additional internal bus
cycles must be accounted for to allow data to be written to the SPI module by the CPU.
118 Peripheral Information and Electrical Specifications
Copyright © 2010–2014, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: AM1707