AM1707_14 Datasheet, PDF (51/201 Pages) Texas Instruments – Microprocessor

www.ti.com
AM1707
SPRS637E – FEBRUARY 2010 – REVISED JUNE 2014
6.6.2 Device Clock Generation
PLL0 is controlled by PLL Controller 0. The PLLC0 manages the clock ratios, alignment, and gating for the
system clocks to the chip. The PLLC is responsible for controlling all modes of the PLL through software,
in terms of pre-division of the clock inputs, multiply factor within the PLL, and post-division for each of the
chip-level clocks from the PLL output. The PLLC also controls reset propagation through the chip, clock
alignment, and test points.
6.6.3 PLL Controller 0 Registers
BYTE
ADDRESS
0x01C1 1000
0x01C1 10E4
0x01C1 1100
0x01C1 1104
0x01C1 1110
0x01C1 1114
0x01C1 1118
0x01C1 111C
0x01C1 1120
0x01C1 1124
0x01C1 1128
0x01C1 1138
0x01C1 113C
0x01C1 1140
0x01C1 1144
0x01C1 1148
0x01C1 114C
0x01C1 1150
0x01C1 1160
0x01C1 1164
0x01C1 1168
0x01C1 116C
Table 6-5. PLL Controller 0 Registers
ACRONYM
REVID
RSTYPE
PLLCTL
OCSEL
PLLM
PREDIV
PLLDIV1
PLLDIV2
PLLDIV3
OSCDIV
POSTDIV
PLLCMD
PLLSTAT
ALNCTL
DCHANGE
CKEN
CKSTAT
SYSTAT
PLLDIV4
PLLDIV5
PLLDIV6
PLLDIV7
REGISTER DESCRIPTION
Revision Identification Register
Reset Type Status Register
PLL Control Register
OBSCLK Select Register
PLL Multiplier Control Register
PLL Pre-Divider Control Register
PLL Controller Divider 1 Register
PLL Controller Divider 2 Register
PLL Controller Divider 3 Register
Oscillator Divider 1 Register (OBSCLK)
PLL Post-Divider Control Register
PLL Controller Command Register
PLL Controller Status Register
PLL Controller Clock Align Control Register
PLLDIV Ratio Change Status Register
Clock Enable Control Register
Clock Status Register
SYSCLK Status Register
PLL Controller Divider 4 Register
PLL Controller Divider 5 Register
PLL Controller Divider 6 Register
PLL Controller Divider 7 Register
Copyright © 2010–2014, Texas Instruments Incorporated
Peripheral Information and Electrical Specifications
51
Submit Documentation Feedback
Product Folder Links: AM1707