AM1707_14 Datasheet, PDF (50/201 Pages) Texas Instruments – Microprocessor

AM1707
SPRS637E – FEBRUARY 2010 – REVISED JUNE 2014
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Table 6-4. Allowed PLL Operating Conditions
No.
PARAMETER
1
PLLRST: Assertion time during
initialization
Lock time: The time that the application
2
has to wait for the PLL to acquire locks
before setting PLLEN, after changing
PREDIV, PLLM, or OSCIN
Default
Value
N/A
N/A
MIN
1000
N/A
MAX
N/A
Max PLL Lock Time = ^{2000 N}
m
where N = Pre-Divider Ratio
M = PLL Multiplier
UNIT
ns
OSCIN
cycles
3
PREDIV
4
PLL input frequency
( PLLREF)
5
PLL multiplier values (PLLM) ⁽¹⁾
6
PLL output frequency. ( PLLOUT )
7
POSTDIV
/1
/1
12
x20
x4
N/A
300
/1
/1
/32
30 (if internal oscillator is used)
50 (if external clock source is used)
x32
600
/32
MHz
MHz
(1) The multiplier values must be chosen such that the PLL output frequency (at PLLOUT) is between 300 and 600 MHz, but the frequency
going into the SYSCLK dividers (after the post divider) cannot exceed the maximum clock frequency defined for the device at a given
voltage operating point.
50
Peripheral Information and Electrical Specifications
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