AM1707_14 Datasheet, PDF (168/201 Pages) Texas Instruments – Microprocessor

AM1707
SPRS637E – FEBRUARY 2010 – REVISED JUNE 2014
Table 6-96. Universal Serial Bus OTG (USB0) Registers (continued)
BYTE ADDRESS
0x01E0 1840
0x01E0 1848
0x01E0 184C
0x01E0 1850
0x01E0 1860
0x01E0 1868
0x01E0 186C
0x01E0 1870
0x01E0 2000
0x01E0 2800
0x01E0 2804
...
0x01E0 28FC
0x01E0 4000
0x01E0 4008
0x01E0 4020
0x01E0 4024
0x01E0 4028
0x01E0 402C
0x01E0 4080
0x01E0 4084
0x01E0 4088
0x01E0 4090
0x01E0 4094
0x01E0 5000
0x01E0 5004
0x01E0 5010
0x01E0 5014
...
0x01E0 50F0
0x01E0 50F4
0x01E0 600C
0x01E0 601C
...
0x01E0 63FC
0x01E0 6800
0x01E0 6804
0x01E0 6808
0x01E0 6810
0x01E0 6814
0x01E0 6818
...
0x01E0 6BF0
0x01E0 6BF4
0x01E0 6BF8
ACRONYM
REGISTER DESCRIPTION
TXGCR[2]
Transmit Channel 2 Global Configuration Register
RXGCR[2]
Receive Channel 2 Global Configuration Register
RXHPCRA[2]
Receive Channel 2 Host Packet Configuration Register A
RXHPCRB[2]
Receive Channel 2 Host Packet Configuration Register B
TXGCR[3]
Transmit Channel 3 Global Configuration Register
RXGCR[3]
Receive Channel 3 Global Configuration Register
RXHPCRA[3]
Receive Channel 3 Host Packet Configuration Register A
RXHPCRB[3]
Receive Channel 3 Host Packet Configuration Register B
DMA_SCHED_CTRL DMA Scheduler Control Register
WORD[0]
DMA Scheduler Table Word 0
WORD[1]
DMA Scheduler Table Word 1
...
...
WORD[63]
DMA Scheduler Table Word 63
QUEUE MANAGER REGISTERS
QMGRREVID
Queue Manager Revision Register
DIVERSION
Queue Diversion Register
FDBSC0
Free Descriptor/Buffer Starvation Count Register 0
FDBSC1
Free Descriptor/Buffer Starvation Count Register 1
FDBSC2
Free Descriptor/Buffer Starvation Count Register 2
FDBSC3
Free Descriptor/Buffer Starvation Count Register 3
LRAM0BASE
Linking RAM Region 0 Base Address Register
LRAM0SIZE
Linking RAM Region 0 Size Register
LRAM1BASE
Linking RAM Region 1 Base Address Register
PEND0
Queue Pending Register 0
PEND1
Queue Pending Register 1
QMEMRBASE[0]
Memory Region 0 Base Address Register
QMEMRCTRL[0]
Memory Region 0 Control Register
QMEMRBASE[1]
Memory Region 1 Base Address Register
QMEMRCTRL[1]
Memory Region 1 Control Register
...
...
QMEMRBASE[15]
Memory Region 15 Base Address Register
QMEMRCTRL[15]
Memory Region 15 Control Register
CTRLD[0]
Queue Manager Queue 0 Control Register D
CTRLD[1]
Queue Manager Queue 1 Control Register D
...
...
CTRLD[63]
Queue Manager Queue 63 Status Register D
QSTATA[0]
Queue Manager Queue 0 Status Register A
QSTATB[0]
Queue Manager Queue 0 Status Register B
QSTATC[0]
Queue Manager Queue 0 Status Register C
QSTATA[1]
Queue Manager Queue 1 Status Register A
QSTATB[1]
Queue Manager Queue 1 Status Register B
QSTATC[1]
Queue Manager Queue 1 Status Register C
...
...
QSTATA[63]
Queue Manager Queue 63 Status Register A
QSTATB[63]
Queue Manager Queue 63 Status Register B
QSTATC[63]
Queue Manager Queue 63 Status Register C
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168 Peripheral Information and Electrical Specifications
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