AM1707_14 Datasheet, PDF (42/201 Pages) Texas Instruments – Microprocessor

AM1707
SPRS637E – FEBRUARY 2010 – REVISED JUNE 2014
www.ti.com
6.2 Recommended Clock and Control Signal Transition Behavior
All clocks and control signals must transition between V_IH and V_IL (or between V_IL and V_IH) in a monotonic
manner.
6.3 Power Supplies
6.3.1 Power-on Sequence
The device should be powered-on in the following order:
1. RTC (RTC_CVDD) may be powered from an external device (such as a battery) prior to all other
supplies being applied or powered-up at the same time as CVDD. If the RTC is not used, RTC_CVDD
should be connected to CVDD. RTC_CVDD should not be left unpowered while CVDD is powered.
2. Core logic supplies:
(a) CVDD core logic supply
(b) Other 1.2V logic supplies (PLL0_VDDA). Groups 2a) and 2b) may be powered up together or 2a)
first followed by 2b).
3. All 1.8V IO supplies (USB0_VDDA18, USB1_VDDA18).
4. All digital IO and analog 3.3V PHY supplies (DVDD, USB0_VDDA33 , USB1_VDDA33).
USB0_VDDA33 and USB1_VDDA33 are not required if both USB0 and USB1 are not used) and may
be left unconnected.
Group 3) and group 4) may be powered on in either order [3 then 4, or 4 then 3] but group 4) must be
powered-on after the core logic supplies.
There is no specific required voltage ramp rate for any of the supplies.
RESET must be maintained active until all power supplies have reached their nominal values.
6.3.2 Power-off Sequence
The power supplies can be powered-off in any order as long as the 3.3V supplies do not remain powered
with the other supplies unpowered.
42
Peripheral Information and Electrical Specifications
Copyright © 2010–2014, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: AM1707