MSP430FR5994_17 Datasheet, PDF (8/168 Pages) Texas Instruments – Mixed-Signal Microcontrollers

MSP430FR5994, MSP430FR59941, MSP430FR5992, MSP430FR5964, MSP430FR5962
SLASE54A – MARCH 2016 – REVISED OCTOBER 2016
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4 Terminal Configuration and Functions
4.1 Pin Diagrams
Figure 4-1 shows the bottom view of the pinout of the 87-pin ZVW package, and Figure 4-2 shows the top
view of the pinout.
DGND P2.0 P2.1 P8.1 P3.5 P1.6 P5.0 P5.3 DVSS1 DVCC1 DGND
L1 L2 L3 L4 L5 L6 L7 L8 L9 L10 L11
DVCC3 DGND P2.2 P8.2 P3.4 P1.7 P5.1 P5.2 P4.6 DGND P2.4
K1 K2 K3 K4 K5 K6 K7 K8 K9 K10 K11
DVSS3 RST
J1 J2
P5.4 P2.3
J10 J11
P2.6 TST
H1 H2
P8.3 P3.6 P3.7 P4.4 P4.5
H4 H5 H6 H7 H8
P5.5 HFIN
H10 H11
P4.2 P4.3
G1 G2
P2.5
G4
P5.7
G8
P5.6 HFOUT
G10 G11
P4.0 P7.7
F1 F2
P4.1
F4
P6.4
F8
P6.5 P2.7
F10 F11
P7.4 P7.5
E1 E2
P7.6
E4
P6.6
E8
AVSS3 LFIN
E10 E11
P7.2 PJ.3
D1 D2
P7.3 P8.0 P4.7 P6.1 P6.0
D4 D5 D6 D7 D8
AVSS2 LFOUT
D10 D11
PJ.1 PJ.2
C1 C2
P6.7 AVSS1
C10 C11
PJ.0
B1
P1.4 P1.5 P7.1 P6.3 P3.2 P3.1 P1.2 AGND AVCC1
B3 B4 B5 B6 B7 B8 B9 B10 B11
DGND DVSS2 DVCC2 P1.3 P7.0 P6.2 P3.3 P3.0 P1.1 P1.0 AGND
A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11
NOTE: On devices with UART BSL: P2.0 is BSLTX, P2.1 is BSLRX
NOTE: On devices with I²C BSL: P1.6 is BSLSDA, P1.7 is BSLSCL
Figure 4-1. 87-Pin ZVW Package (Bottom View)
8
Terminal Configuration and Functions
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