English
Language : 

MSP430FR5994_17 Datasheet, PDF (121/168 Pages) Texas Instruments – Mixed-Signal Microcontrollers
www.ti.com
MSP430FR5994, MSP430FR59941, MSP430FR5992, MSP430FR5964, MSP430FR5962
SLASE54A – MARCH 2016 – REVISED OCTOBER 2016
Table 6-38. Port PJ (PJ.0 to PJ.3) Pin Functions
PIN NAME (PJ.x)
x
PJ.0 (I/O)(2)
TDO (3)
FUNCTION
CONTROL BITS OR SIGNALS(1)
PJDIR.x
PJSEL1.x PJSEL0.x CEPDx (Cx)
I: 0; O: 1
0
0
0
X
X
X
0
PJ.0/TDO/TB0OUTH/
SMCLK/SRSCG1/C6
TB0OUTH
SMCLK (4)
0 N/A
CPU Status Register Bit SCG1
0
0
1
0
1
0
1
0
0
1
N/A
Internally tied to DVSS
C6 (5)
PJ.1 (I/O)(2)
TDI/TCLK(3) (6)
0
1
1
0
1
X
X
X
1
I: 0; O: 1
0
0
0
X
X
X
0
PJ.1/TDI/TCLK/MCLK/
SRSCG0/C7
N/A
MCLK
1 N/A
CPU Status Register Bit SCG0
0
0
1
0
1
0
1
0
0
1
N/A
Internally tied to DVSS
C7 (5)
PJ.2 (I/O)(2)
TMS(3) (6)
0
1
1
0
1
X
X
X
1
I: 0; O: 1
0
0
0
X
X
X
0
PJ.2/TMS/ACLK/
SROSCOFF/C8
N/A
ACLK
2 N/A
CPU Status Register Bit OSCOFF
0
0
1
0
1
0
1
0
0
1
N/A
Internally tied to DVSS
C8 (5)
PJ.3 (I/O)(2)
TCK (3) (6)
0
1
1
0
1
X
X
X
1
I: 0; O: 1
0
0
0
X
X
X
0
N/A
Internally tied to DVSS
0
0
1
0
1
PJ.3/TCK/SRCPUOFF/C9
3 N/A
CPU Status Register Bit CPUOFF
0
1
0
0
1
N/A
Internally tied to DVSS
C9 (5)
0
1
1
0
1
X
X
X
1
(1) X = Don't care
(2) Default condition
(3) The pin direction is controlled by the JTAG module. JTAG mode selection is made through the SYS module or by the Spy-Bi-Wire four-
wire entry sequence. Neither PJSEL1.x and PJSEL0.x nor CEPDx bits have an effect in these cases.
(4) Do not use this pin as SMCLK output if the TB0OUTH functionality is used on any other pin. Select an alternate SMCLK output pin.
(5) Setting the CEPDx bit of the comparator disables the output driver and the input Schmitt trigger to prevent parasitic cross currents when
applying analog signals. Selecting the Cx input pin to the comparator multiplexer with the input select bits in the comparator module
automatically disables The output driver and input buffer for that pin, regardless of the state of the associated CEPDx bit.
(6) In JTAG mode, pullups are activated automatically on TMS, TCK, and TDI/TCLK. PJREN.x are don't care.
Copyright © 2016, Texas Instruments Incorporated
Detailed Description 121
Submit Documentation Feedback
Product Folder Links: MSP430FR5994 MSP430FR59941 MSP430FR5992 MSP430FR5964 MSP430FR5962