MSP430FR5994_17 Datasheet, PDF (116/168 Pages) Texas Instruments – Mixed-Signal Microcontrollers

MSP430FR5994, MSP430FR59941, MSP430FR5992, MSP430FR5964, MSP430FR5962
SLASE54A – MARCH 2016 – REVISED OCTOBER 2016
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Table 6-36. Port PJ (PJ.4 and PJ.5) Pin Functions
PIN NAME (PJ.x) x
FUNCTION
PJDIR.x
CONTROL BITS AND SIGNALS⁽¹⁾
PJSEL1.5 PJSEL0.5 PJSEL1.4 PJSEL0.4
LFXT
BYPASS
PJ.4 (I/O)
I: 0; O: 1
X
X
0
0
X
PJ.4/LFXIN
N/A
0
X
X
1
X
X
4 Internally tied to DVSS
1
LFXIN crystal mode⁽²⁾
X
X
X
0
1
0
LFXIN bypass mode⁽²⁾
X
X
X
0
1
1
PJ.5 (I/O)
0
0
0
I: 0; O: 1
0
0
1
X
X
X
1 ⁽³⁾
PJ.5/LFXOUT
N/A
5
0
0
see ⁽⁴⁾
see ⁽⁴⁾
1
X
0
0
X
X
1 ⁽³⁾
0
Internally tied to DVSS
1
see ⁽⁴⁾
see ⁽⁴⁾
1
X
LFXOUT crystal mode⁽²⁾
X
X
X
0
0
0
X
X
1 ⁽³⁾
1
0
(1) X = Don't care
(2) If PJSEL1.4 = 0 and PJSEL0.4 = 1, the general-purpose I/O is disabled. When LFXTBYPASS = 0, PJ.4 and PJ.5 are configured for
crystal operation and PJSEL1.5 and PJSEL0.5 are don't care. When LFXTBYPASS = 1, PJ.4 is configured for bypass operation and
PJ.5 is configured as general-purpose I/O.
(3) When PJ.4 is configured in bypass mode, PJ.5 is configured as general-purpose I/O.
(4) If PJSEL0.5 = 1 or PJSEL1.5 = 1, the general-purpose I/O functionality is disabled. No input function is available. Configured as output,
the pin is actively pulled to zero.
116 Detailed Description
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