MSP430FR5994_17 Datasheet, PDF (49/168 Pages) Texas Instruments – Mixed-Signal Microcontrollers

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MSP430FR5994, MSP430FR59941, MSP430FR5992, MSP430FR5964, MSP430FR5962
SLASE54A – MARCH 2016 – REVISED OCTOBER 2016
Table 5-20 lists the SPI master mode operating characteristics.
Table 5-20. eUSCI (SPI Master Mode)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)⁽¹⁾
PARAMETER
TEST CONDITIONS
V_CC
MIN TYP MAX UNIT
t_STE,LEAD STE lead time, STE active to clock UCSTEM = 1, UCMODEx = 01 or 10
1
UCxCLK
cycles
t_STE,LAG
STE lag time, Last clock to STE
inactive
UCSTEM = 1, UCMODEx = 01 or 10
1
UCxCLK
cycles
t_STE,ACC
STE access time, STE active to
SIMO data out
UCSTEM = 0, UCMODEx = 01 or 10
2.2 V,
3.0 V
60 ns
t_STE,DIS
STE disable time, STE inactive to
SOMI high impedance
UCSTEM = 0, UCMODEx = 01 or 10
2.2 V,
3.0 V
80 ns
t_SU,MI
SOMI input data setup time
2.2 V
40
ns
3.0 V
40
t_HD,MI
SOMI input data hold time
2.2 V
0
ns
3.0 V
0
t_VALID,MO SIMO output data valid time⁽²⁾
UCLK edge to SIMO valid,
C_L = 20 pF
2.2 V
3.0 V
11
ns
10
t_HD,MO
SIMO output data hold time⁽³⁾
C_L = 20 pF
2.2 V
3.0 V
0
ns
0
(1) f_UCxCLK = 1/2t_LO/HI with tL_O/HI = max(t_{VALID,MO(eUSCI)} + t_SU,SI(Slave), t_SU,MI(eUSCI) + t_{VALID,SO(Slave)}).
For the slave parameters t_SU,SI(Slave) and t_{VALID,SO(Slave)}, see the SPI parameters of the attached slave.
(2) Specifies the time to drive the next valid data to the SIMO output after the output changing UCLK clock edge. See the timing diagrams
in Figure 5-10 and Figure 5-11.
(3) Specifies how long data on the SIMO output is valid after the output changing UCLK clock edge. Negative values indicate that the data
on the SIMO output can become invalid before the output changing clock edge observed on UCLK. See the timing diagrams in Figure 5-
10 and Figure 5-11.
Copyright © 2016, Texas Instruments Incorporated
Specifications
49
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