MSP430FR5994_17 Datasheet, PDF (76/168 Pages) Texas Instruments – Mixed-Signal Microcontrollers

MSP430FR5994, MSP430FR59941, MSP430FR5992, MSP430FR5964, MSP430FR5962
SLASE54A – MARCH 2016 – REVISED OCTOBER 2016
www.ti.com
Table 6-10. System Module Interrupt Vector Registers (continued)
INTERRUPT VECTOR
REGISTER
ADDRESS
SYSUNIV, User NMI
019Ah
INTERRUPT EVENT
No interrupt pending
NMIIFG NMI pin
OFIFG oscillator fault
Reserved
Reserved
Reserved
VALUE
00h
02h
04h
06h
08h
0Ah to 1Eh
PRIORITY
Highest
Lowest
6.12.8 DMA Controller
The DMA controller allows movement of data from one memory address to another without CPU
intervention. For example, the DMA controller can be used to move data from the ADC12_B conversion
memory to RAM. Using the DMA controller can increase the throughput of peripheral modules. The DMA
controller reduces system power consumption by allowing the CPU to remain in sleep mode, without
having to awaken to move data to or from a peripheral. See Table 6-66 for control and configuration
registers. Table 6-11 lists the available DMA triggers.
Table 6-11. DMA Trigger Assignments⁽¹⁾
TRIGGER
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
CHANNEL 0
DMAREQ
TA0CCR0 CCIFG
TA0CCR2 CCIFG
TA1CCR0 CCIFG
TA1CCR2 CCIFG
TA2CCR0 CCIFG
TA3CCR0 CCIFG
TB0CCR0 CCIFG
TB0CCR2 CCIFG
TA4CCR0 CCIFG
Reserved
AES Trigger 0
AES Trigger 1
AES Trigger 2
UCA0RXIFG
UCA0TXIFG
UCA1RXIFG
UCA1TXIFG
UCB0RXIFG (SPI)
UCB0RXIFG0 (I²C)
UCB0TXIFG (SPI)
UCB0TXIFG0 (I²C)
UCB0RXIFG1 (I²C)
UCB0TXIFG1 (I²C)
UCB0RXIFG2 (I²C)
UCB0TXIFG2 (I²C)
UCB0RXIFG3 (I²C)
UCB0TXIFG3 (I²C)
ADC12 end of
conversion
LEA ready⁽²⁾
CHANNEL 1
DMAREQ
TA0CCR0 CCIFG
TA0CCR2 CCIFG
TA1CCR0 CCIFG
TA1CCR2 CCIFG
TA2CCR0 CCIFG
TA3CCR0 CCIFG
TB0CCR0 CCIFG
TB0CCR2 CCIFG
TA4CCR0 CCIFG
Reserved
AES Trigger 0
AES Trigger 1
AES Trigger 2
UCA0RXIFG
UCA0TXIFG
UCA1RXIFG
UCA1TXIFG
UCB0RXIFG (SPI)
UCB0RXIFG0 (I²C)
UCB0TXIFG (SPI)
UCB0TXIFG0 (I²C)
UCB0RXIFG1 (I²C)
UCB0TXIFG1 (I²C)
UCB0RXIFG2 (I²C)
UCB0TXIFG2 (I²C)
UCB0RXIFG3 (I²C)
UCB0TXIFG3 (I²C)
ADC12 end of
conversion
LEA ready⁽²⁾
CHANNEL 2
DMAREQ
TA0CCR0 CCIFG
TA0CCR2 CCIFG
TA1CCR0 CCIFG
TA1CCR2 CCIFG
TA2CCR0 CCIFG
TA3CCR0 CCIFG
TB0CCR0 CCIFG
TB0CCR2 CCIFG
TA4CCR0 CCIFG
Reserved
AES Trigger 0
AES Trigger 1
AES Trigger 2
UCA0RXIFG
UCA0TXIFG
UCA1RXIFG
UCA1TXIFG
UCB0RXIFG (SPI)
UCB0RXIFG0 (I²C)
UCB0TXIFG (SPI)
UCB0TXIFG0 (I²C)
UCB0RXIFG1 (I²C)
UCB0TXIFG1 (I²C)
UCB0RXIFG2 (I²C)
UCB0TXIFG2 (I²C)
UCB0RXIFG3 (I²C)
UCB0TXIFG3 (I²C)
ADC12 end of
conversion
LEA ready⁽²⁾
CHANNEL 3
DMAREQ
TA0CCR0 CCIFG
TA0CCR2 CCIFG
TA1CCR0 CCIFG
TA1CCR2 CCIFG
TA2CCR0 CCIFG
TA3CCR0 CCIFG
TB0CCR0 CCIFG
TB0CCR2 CCIFG
TA4CCR0 CCIFG
Reserved
AES Trigger 0
AES Trigger 1
AES Trigger 2
UCA2RXIFG
UCA2TXIFG
UCA3RXIFG
UCA3TXIFG
UCB1RXIFG (SPI)
UCB1RXIFG0 (I²C)
UCB1TXIFG (SPI)
UCB1TXIFG0 (I²C)
UCB1RXIFG1 (I²C)
UCB1TXIFG1 (I²C)
UCB1RXIFG2 (I²C)
UCB1TXIFG2 (I²C)
UCB1RXIFG3 (I²C)
UCB1TXIFG3 (I²C)
ADC12 end of
conversion
LEA ready⁽²⁾
CHANNEL 4
DMAREQ
TA0CCR0 CCIFG
TA0CCR2 CCIFG
TA1CCR0 CCIFG
TA1CCR2 CCIFG
TA2CCR0 CCIFG
TA3CCR0 CCIFG
TB0CCR0 CCIFG
TB0CCR2 CCIFG
TA4CCR0 CCIFG
Reserved
AES Trigger 0
AES Trigger 1
AES Trigger 2
UCA2RXIFG
UCA2TXIFG
UCA3RXIFG
UCA3TXIFG
UCB2RXIFG (SPI)
UCB2RXIFG0 (I²C)
UCB2TXIFG (SPI)
UCB2TXIFG0 (I²C)
UCB2RXIFG1 (I²C)
UCB2TXIFG1 (I²C)
UCB2RXIFG2 (I²C)
UCB2TXIFG2 (I²C)
UCB2RXIFG3 (I²C)
UCB2TXIFG3 (I²C)
ADC12 end of
conversion
LEA ready⁽²⁾
CHANNEL 5
DMAREQ
TA0CCR0 CCIFG
TA0CCR2 CCIFG
TA1CCR0 CCIFG
TA1CCR2 CCIFG
TA2CCR0 CCIFG
TA3CCR0 CCIFG
TB0CCR0 CCIFG
TB0CCR2 CCIFG
TA4CCR0 CCIFG
Reserved
AES Trigger 0
AES Trigger 1
AES Trigger 2
UCA2RXIFG
UCA2TXIFG
UCA3RXIFG
UCA3TXIFG
UCB3RXIFG (SPI)
UCB3RXIFG0 (I²C)
UCB3TXIFG (SPI)
UCB3TXIFG0 (I²C)
UCB3RXIFG1 (I²C)
UCB3TXIFG1 (I²C)
UCB3RXIFG2 (I²C)
UCB3TXIFG2 (I²C)
UCB3RXIFG3 (I²C)
UCB3TXIFG3 (I²C)
ADC12 end of
conversion
LEA ready⁽²⁾
(1) If a reserved trigger source is selected, no trigger is generated.
(2) Reserved on MSP430FR596x.
76
Detailed Description
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