MSP430FR5994_17 Datasheet, PDF (10/168 Pages) Texas Instruments – Mixed-Signal Microcontrollers

MSP430FR5994, MSP430FR59941, MSP430FR5992, MSP430FR5964, MSP430FR5962
SLASE54A – MARCH 2016 – REVISED OCTOBER 2016
Figure 4-3 shows the pinout of the 80-pin PN package.
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P1.0/TA0.1/DMAE0/RTCCLK/A0/C0/VREF-/VeREF-
P1.1/TA0.2/TA1CLK/COUT/A1/C1/VREF+/VeREF+
P1.2/TA1.1/TA0CLK/COUT/A2/C2
P3.0/A12/C12
P3.1/A13/C13
P3.2/A14/C14
P3.3/A15/C15
P6.0/UCA3TXD/UCA3SIMO
P6.1/UCA3RXD/UCA3SOMI
P6.2/UCA3CLK
P6.3/UCA3STE
P4.7
P7.0/UCB2SIMO/UCB2SDA
P7.1/UCB2SOMI/UCB2SCL
P8.0
P1.3/TA1.2/UCB0STE/A3/C3
P1.4/TB0.1/UCA0STE/A4/C4
P1.5/TB0.2/UCA0CLK/A5/C5
DVSS2
DVCC2
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61
1
60
2
59
3
58
4
57
5
56
6
55
7
54
8
53
9
52
10
51
11
50
12
49
13
48
14
47
15
46
16
45
17
44
18
43
19
42
20
41
21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
DVSS1
P4.6
P4.5
P4.4/TB0.5
P5.3/UCB1STE
P5.2/UCB1CLK/TA4CLK
P5.1/UCB1SOMI/UCB1SCL
P5.0/UCB1SIMO/UCB1SDA
P1.7/TB0.4/UCB0SOMI/UCB0SCL/TA1.0
P1.6/TB0.3/UCB0SIMO/UCB0SDA/TA0.0
P3.7/TB0.6
P3.6/TB0.5
P3.5/TB0.4/COUT
P3.4/TB0.3/SMCLK
P8.3
P8.2
P8.1
P2.2/TB0.2/UCB0CLK
P2.1/TB0.0/UCA0RXD/UCA0SOMI
P2.0/TB0.6/UCA0TXD/UCA0SIMO/TB0CLK/ACLK
NOTE: On devices with UART BSL: P2.0 is BSLTX, P2.1 is BSLRX
NOTE: On devices with I²C BSL: P1.6 is BSLSDA, P1.7 is BSLSCL
Figure 4-3. 80-Pin PN Package (Top View)
10
Terminal Configuration and Functions
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