MSP430FR5994_17 Datasheet, PDF (120/168 Pages) Texas Instruments – Mixed-Signal Microcontrollers

MSP430FR5994, MSP430FR59941, MSP430FR5992, MSP430FR5964, MSP430FR5962
SLASE54A – MARCH 2016 – REVISED OCTOBER 2016
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6.13.20 Port PJ (PJ.0 to PJ.3) JTAG Pins TDO, TMS, TCK, TDI/TCLK, Input/Output With
Schmitt Trigger
Figure 6-23 shows the port diagram. Table 6-38 summarizes the selection of the pin functions.
To Comparator
From Comparator
CBPD.x
JTAG enable
From JTAG
From JTAG
PJREN.x
PJDIR.x
00
1
01
0
10
11
Direction
0: Input
1: Output
Pad Logic
DVSS
0
DVCC
1
1
PJOUT.x
00
From module 1
01
1
From Status Register (SR)
10
0
DVSS
11
PJSEL1.x
PJSEL0.x
PJIN.x
EN
To modules
D
and JTAG
Bus
Keeper
NOTE: Functional representation only.
Figure 6-23. Port PJ (PJ.0 to PJ.3) Diagram
PJ.0/TDO/TB0OUTH/SMCLK/
SRSCG1/C6
PJ.1/TDI/TCLK/MCLK/
SRSCG0/C7
PJ.2/TMS/ACLK/
SROSCOFF/C8
PJ.3/TCK/
SRCPUOFF/C9
120 Detailed Description
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