DS90UR908Q_14 Datasheet, PDF (8/33 Pages) Texas Instruments – 5 - 65 MHz 24-bit Color FPD-Link II to FPD-Link Converter

DS90UR908Q
SNLS317H – SEPTEMBER 2009 – REVISED APRIL 2013
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Switching Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
Parameter
Conditions
Pin/Freq.
Min
FPD-Link II
SSC[2:0] = 000
5 MHz
t_DDLT
Lock Time, Figure 7⁽¹⁾
SSC[2:0] = 111
SSC[2:0] = 000
5 MHz
65 MHz
SSC[2:0] = 111
65 MHz
Input Jitter Frequency <
EQ = Off
2 MHz
t_IJIT
Input Jitter Tolerance, Figure 10 SSC[2:0] = 000
TxCLKOUT± = 65 MHz
Input Jitter Frequency >
6 MHz
FPD-Link Output
t_TLHT
t_THLT
t_DCCJ
Low to High Transition Time
High to Low Transition Time
Cycle-to-Cycle Output
Jitter ^{(2) (3) (4)}
R_L = 100Ω
5 MHz
65 MHz
TxCLKOUT±,
TxOUT[3:0]±
TxCLKOUT±
t_TTP1
Transmitter Pulse Position for
bit 1
t_TTP0
Transmitter Pulse Position for
bit 0
t_TPP6
Transmitter Pulse Position for
bit 6
t_TTP5
Transmitter Pulse Position for
bit 5
5 - 65 MHz, Figure 9
TxOUT[3:0]±
t_TTP4
Transmitter Pulse Position for
bit 4
t_TTP3
Transmitter Pulse Position for
bit 3
t_TTP2
Transmitter Pulse Position for
bit 2
Δt_TTP
Offset Transmitter Pulse
Position (bit 6— bit 0)
65 MHz, Figure 9
t_DD
t_TPDD
Delay-Latency
Power Down Delay, active to
OFF
SeeFigure 4
65 MHz, Figure 5
t_TXZR Enable Delay, OFF to active
LVCMOS Outputs
65 MHz, Figure 6
t_CLH
t_CHL
t_PASS
Low to High Transition Time
High to Low Transition Time
BIST PASS Valid Time,
BISTEN = 1, Figure 11
C_L = 8 pF, Figure 3
5 MHz
65 MHz
LOCK, PASS
PASS
SSCG Mode
f_DEV
Spread Spectrum
Clocking Deviation
Frequency
See ⁽⁴⁾
TxCLKOUT = 5 to 65
MHz,
±0.5
SSC[2:0] = ON
f_MOD
Spread Spectrum
Clocking Modulation
Frequency
See ⁽⁴⁾
TxCLKOUT = 5 to 65
MHz,
8
SSC[2:0] = ON
Typ
Max Units
7
ms
14
ms
6
ms
8
ms
>0.9
UI
> 0.5
UI
0.3
0.6
ns
0.3
0.6
ns
900 2100 ps
75
125
ps
1
UI
2
UI
3
UI
4
UI
5
UI
6
UI
7
UI
< +0.1
UI
10*T
T
7
12
ns
40
55
ns
5
15
ns
5
15
ns
570
580
ns
50
65
ns
±2
%
100 kHz
(1) t_PLD and t_DDLT is the time required by the serializer and deserializer to obtain lock when exiting power-down state with an active PCLK.
(2) t_DCCJ is the maximum amount of jitter between adjacent clock cycles.
(3) Specification is ensured by characterization and is not tested in production.
(4) Specification is ensured by design and is not tested in production.
8
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