DS90UR908Q_14 Datasheet, PDF (14/33 Pages) Texas Instruments – 5 - 65 MHz 24-bit Color FPD-Link II to FPD-Link Converter

DS90UR908Q
SNLS317H – SEPTEMBER 2009 – REVISED APRIL 2013
www.ti.com
Functional Description
The DS90UR908Q receives 27-bits of data (24-high speed bits and 3 low speed bits) over a single serial FPD-
Link II pair operating at 140Mbps to 1.82Gbps. The serial stream contains an embedded clock, video control
signals and the DC-balance information which enhances signal quality and supports AC coupling. The receiver
converts the serial stream into a 5-channel (4 data and 1 clock) FPD-Link LVDS Interface. The device is intended
to be used with the DS90UR907Q or the DS90UR905Q FPD-Link II serializers, but is backward compatible with
previous generation of FPD-Link II as well.
The device converts a single input serial data stream to a FPD-Link output bus, and also provides a signal check
for the chipset Built In Self Test (BIST) mode. The device can be configured via external pins or through the
optional serial control bus. It features enhance signal quality on the link by supporting the FPD-Link II data
coding that provides randomization, scrambling, and DC balancing of the data. It also includes multiple features
to reduce EMI associated with display data transmission. This includes the randomization and scrambling of the
data, FPD-Link LVDS Output interface, and also the output spread spectrum clock generation (SSCG) support.
The power saving features include a power down mode, and optional LVCMOS (1.8 V) interface compatibility.
The DS90UR908Q can lock to a data stream without the use of a separate reference clock source, which greatly
simplifies system complexity and overall cost. It also synchronizes to the serializer regardless of the data pattern,
delivering true automatic “plug and lock” performance. It can lock to the incoming serial stream without the need
of special training patterns or sync characters. The DS90UR908Q recovers the clock and data by extracting the
embedded clock information, validating and then deserializing the incoming data stream.
The DS90UR907Q / DS90UR908Q chipset supports 24-bit color depth, HS, VS and DE video control signals and
up to three over-sampled low-speed (general purpose) data bits.
DATA TRANSFER
The DS90UR908Q will receive a pixel of data in the following format: C1 and C0 represent the embedded clock
in the serial stream. C1 is always HIGH and C0 is always LOW. b[23:0] contain the scrambled data. DCB is the
DC-Balanced control bit. DCB is used to minimize the short and long-term DC bias on the signal lines. This bit
determines if the data is unmodified or inverted. DCA is used to validate data integrity in the embedded data
stream. Both DCA and DCB coding schemes are generated by the Ser and decoded by the Des automatically.
Figure 13 illustrates the serial stream per PCLK cycle.
Note: The figure only illustrates the bits but does not actually represent the bit location as the bits are scrambled
and balanced continuously.
C
1
b
0
b
1
b
2
b
3
b
4
b
5
b
6
b
7
b
8
b
9
b
1
0
b
1
1
D
C
A
D
C
B
b
1
2
b
1
3
b
1
4
b
1
5
b
1
6
b
1
7
b
1
8
b
1
9
b
2
0
b
2
1
b
2
2
b
2
3
C
0
Figure 13. FPD-Link II Serial Stream
The device supports clocks in the range of 5 MHz to 65 MHz. With every clock cycle 24 bits of payload are
received along with the four overhead bits. Thus, the line rate is 1.82 Gbps maximum (140 Mbps minimum) with
an effective data rate of 1.56 Gbps maximum. The link is extremely efficient at 86% (24/28).
OPERATING MODES AND BACKWARD COMPATIBILITY (CONFIG[1:0])
The DS90UR908Q is backward compatible with previous generations of FPD-Link II serializers. Configuration
modes are provided for backwards compatibility with the DS90C241 FPD-Link II Generation 1, and also the
DS90UR241 or DS99R421 FPD-Link II Generation 2 serializer by setting the respective mode with the
CONFIG[1:0] pins as shown in Table 1. The selection also determine whether the Video Control Signal filter
feature is enabled or disabled in Normal mode. This feature may be controlled by pin or by Register.
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