DS90UR908Q_14 Datasheet, PDF (16/33 Pages) Texas Instruments – 5 - 65 MHz 24-bit Color FPD-Link II to FPD-Link Converter

DS90UR908Q
SNLS317H – SEPTEMBER 2009 – REVISED APRIL 2013
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TxCLKOUT +/-
TxOUT3 +/-
TxOUT2 +/-
TxOUT1 +/-
TxOUT0 +/-
Previous cycle
B[1]
(bit 26)
DE
(bit 20)
VS
(bit 19)
Current cycle
B[0]
(bit 25)
HS
(bit 18)
G[1]
(bit 24)
G[0]
(bit 23)
B[7]
(bit 17)
B[6]
(bit 16)
R[1]
(bit 22)
B[5]
(bit 15)
R[0]
(bit 21)
B[4]
(bit 14)
B[3]
(bit 13)
B[2]
(bit 12)
G[7]
(bit 11)
G[6]
(bit 10)
G[5]
(bit 9)
G[4]
(bit 8)
G[2]
(bit 6)
R[7]
(bit 5)
R[6]
(bit 4)
R[5]
(bit 3)
R[4]
(bit 2)
R[3]
(bit 1)
Figure 15. 8–bit FPD-LInk Mapping: LSB's on TxOUT3
G[3]
(bit 7)
R[2]
(bit 0)
TxCLKOUT +/-
TxOUT3 +/-
Previous cycle
TxOUT2 +/-
Current cycle
B[7]
(bit 26)
B[6]
(bit 25)
G[7]
(bit 24)
G[6]
(bit 23)
R[7]
(bit 22)
DE
(bit 20)
VS
(bit 19)
HS
(bit 18)
B[5]
(bit 17)
B[4]
(bit 16)
B[3]
(bit 15)
R[6]
(bit 21)
B[2]
(bit 14)
TxOUT1 +/-
B[1]
(bit 13)
B[0]
(bit 12)
G[5]
(bit 11)
G[4]
(bit 10)
G[3]
(bit 9)
G[2]
(bit 8)
G[1]
(bit 7)
TxOUT0 +/-
G[0]
(bit 6)
R[5]
(bit 5)
R[4]
(bit 4)
R[3]
(bit 3)
R[2]
(bit 2)
R[1]
(bit 1)
R[0]
(bit 0)
Figure 16. 8–bit FPD-LInk Mapping: MSB's on TxOUT3
FPD-LINK II INPUT
Common Mode Filter Pin (CMF) — Optional
The DS90UR908Q provides access to the center tap of the internal termination. A capacitor may be placed on
this pin for additional common-mode filtering of the differential pair. This can be useful in high noise
environments for additional noise rejection capability. A 4.7 µF capacitor may be connected to this pin to Ground.
Input Equalizer Gain (EQ)
The DS90UR908Q can enable receiver input equalization of the serial stream to compensate the cable loss and
increase the eye opening to the input. The equalization feature may be controlled by the EQ pin (strap option)
Table 4 or by register Table 8.
16
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