DS90UR908Q_14 Datasheet, PDF (3/33 Pages) Texas Instruments – 5 - 65 MHz 24-bit Color FPD-Link II to FPD-Link Converter

DS90UR908Q
www.ti.com
SNLS317H – SEPTEMBER 2009 – REVISED APRIL 2013
PIN DESCRIPTIONS⁽¹⁾
Pin Name
Pin #
I/O, Type
Description
FPD-Link II Input Interface
RIN+
40
I, LVDS
True input
The input must be AC coupled with a 100 nF capacitor. Internal termination.
RIN-
41
I, LVDS
Inverting input
The input must be AC coupled with a 100 nF capacitor. Internal termination.
CMF
42
I, Analog
Common-Mode Filter
VCM center-tap is a virtual ground which maybe ac-coupled to ground to increase receiver
common mode noise immunity. Recommended value is 4.7 μF or higher.
FPD-Link Output Interface
TxOUT[3:0]+ 15,19, 21, O, LVDS
23
True LVDS Data Output
TxOUT[3:0]-
16,20, 22, O, LVDS
24
Inverting LVDS Data Output
TxCLKOUT+ 17
O, LVDS
True LVDS Clock Output
TxCLKOUT- 18
O, LVDS
Inverting LVDS Clock Output
LVCMOS Outputs
LOCK
27
O, LVMOS
LOCK Status Output
LOCK = 1, PLL is locked, output states determined by OEN.
LOCK = 0, PLL is unlocked, output states determined by OSS_SEL and OEN, Table 3
May be used as a Link Status or to flag when the Video Data is active (ON/OFF).
Control and Configuration
PDB
1
I, LVCMOS
w/ pull-down
Power Down Mode Input
PDB = 1, Device is enabled (normal operation)
PDB = 0, Device is in power-down, the outputs are TRI-STATE. Control registers are
RESET.
VODSEL
33
I, LVCMOS FPD-Link Output Voltage Select, Table 4
w/ pull-down VODSEL = 1, LVDS VOD is ±400 mV, 800 mVp-p (typ)
VODSEL = 0, LVDS VOD is ±250 mV, 500 mVp-p (typ)
OEN
30
I, LVCMOS Output Enable Input, Table 3
w/ pull-down
OSS_SEL
35
I, LVCMOS Output Sleep State Select Input, Table 3
w/ pull-down
LFMODE
36
I, LVCMOS Low Frequency Mode — Pin or Register Control
w/ pull-down LF_MODE = 1, low frequency mode (TxCLKOUT = 5-20 MHz)
LF_MODE = 0, high frequency mode (TxCLKOUT = 20-65 MHz)
MAPSEL
34
I, LVCMOS FPD-Link Map Select — Pin or Register Control
w/ pull-down MAPSEL = 1, MSB on TxOUT3+/-, Figure 16
MAPSEL = 0, LSB on TxOUT3+/-, Figure 15
CONFIG[1:0] 11,10
I, LVCMOS
w/ pull-down
Operating Modes — Pin or Register Control
Determine the device operating mode and interfacing device, Table 1
CONFIG[1:0] = 00: Interfacing to DS90UR905Q or DS90UR907Q, Control Signal Filter
DISABLED
CONFIG[1:0] = 01: Interfacing to DS90UR905Q or DS90UR907Q, Control Signal Filter
ENABLED
CONFIG[1:0] = 10: Interfacing to DS90UR241 or DS99R421
CONFIG[1:0] = 11: Interfacing to DS90C241
SSC[2:0]
7, 3, 2
I, LVCMOS Spread Spectrum Clock Generation (SSCG) Range Select, See Table 5 and Table 6
w/ pull-down
RES
37
I, LVCMOS Reserved
w/ pull-down Tie Low
Control and Configuration — STRAP PIN
For a High State, use a 10 kΩ pull up to VDDIO; for a Low State, the IO includes an internal pull down. The STRAP pin is read upon power-
up and set device configuration. Pin number listed along with shared LVCMOS Output name in square bracket.
EQ
28 [PASS] STRAP
EQ Gain Control of FPD-Link II Input
I, LVCMOS EQ = 1, EQ gain is enabled (~13 dB)
w/ pull-down EQ = 0, EQ gain is disabled (~1.625 dB)
(1) 1 = High, 0 = Low
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