DS90UR908Q_14 Datasheet, PDF (21/33 Pages) Texas Instruments – 5 - 65 MHz 24-bit Color FPD-Link II to FPD-Link Converter

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DS90UR908Q
SNLS317H – SEPTEMBER 2009 – REVISED APRIL 2013
BISTEN
(Serializer)
BISTEN
(DS90UR908Q)
TxCLKOUT
(Diff.)
TxOUT[3:0]
(Diff.)
DATA
(internal)
PASS
Prior Result
DATA
X
(internal)
PASS ^{Prior Result}
DATA
X
(internal)
PASS
Prior Result
Normal
PRBS
X = bit error(s)
X
X
X = bit error(s)
X
X
BIST Test
BIST Duration
PASS
FAIL
FAIL
BIST
Result
Held
Normal
Figure 20. BIST Waveforms
Serial Bus Control — Optional
The DS90UR908Q may also be configured by the use of a serial control bus that is I2C protocol compatible. By
default, the I2C reg_0x00'h is set to 00'h and all configuration is set by control/strap pins. A write of 01'h to
reg_0x00'h will enable/allow configuration by registers; this will override the control/strap pins. Multiple devices
may share the serial control bus since multiple addresses are supported. See Figure 21.
The serial bus is comprised of three pins. The SCL is a Serial Bus Clock Input. The SDA is the Serial Bus Data
Input / Output signal. Both SCL and SDA signals require an external pull up resistor to V_DDIO. For most
applications a 4.7 k pull up resistor to V_DDIO may be used. The resistor value may be adjusted for capacitive
loading and data rate requirements. The signals are either pulled High, or driven Low.
1.8V
HOST
SCL
SDA
V_DDIO
4.7k
4.7k
10k
ID[X]
R_ID
DS90UR908Q
SCL
SDA
To other
Devices
Figure 21. Serial Control Bus Connection
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