DS90UR908Q_14 Datasheet, PDF (19/33 Pages) Texas Instruments – 5 - 65 MHz 24-bit Color FPD-Link II to FPD-Link Converter

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DS90UR908Q
SNLS317H – SEPTEMBER 2009 – REVISED APRIL 2013
Frequency
F_PCLK+
F_PCLK
F_PCLK-
fdev(max)
1/fmod
Figure 17. SSCG Waveform
fdev(min)
Time
OSCILLATOR OUTPUT — OPTIONAL
The DS90UR908Q provides an optional TxCLKOUT when the input clock (serial stream) has been lost. This is
based on an internal oscillator. The frequency of the oscillator may be selected. This feature may be controlled
by the external pin and the register. See Table 3, Table 8, and Figure 18.
PDB
RIN
(Diff.)
LOCK
L
TxOUT[3:0]
Z
TxCLKOUT
Z
f
Z
PASS
active serial stream
H
L
Z
f
Z
X
H
L
Z
Z
Z
OFF
OSC Output
Active
OSC Output
CONDITIONS: OEN = H, OSS_SEL = H, and OSC_SEL not equal to 000.
Active
OFF
Figure 18. TxCLKOUT Output Oscillator Option Enabled
Built In Self Test (BIST) — Optional
An optional At-Speed Built In Self Test (BIST) feature supports the testing of the high-speed serial link. This is
useful in the prototype stage, equipment production, in-system test and also for system diagnostics. In the BIST
mode only an input clock is required along with control to the Ser and Des BISTEN input pins. The Ser outputs a
test pattern (PRBS7) and drives the link at speed. The Des detects the PRBS7 pattern and monitors it for errors.
The PASS output pin toggles to flag any payloads that are received with 1 to 24 bit errors. The BISTM pin
selects the operational mode of the PASS pin. If BISTM = L, the PASS pins reports the final result only. If BISTM
= H, the PASS pins counts payload errors and also results the result. The result of the test is held on the PASS
output until reset (new BIST test or Power Down). A high on PASS indicates NO ERRORS were detected. A Low
on PASS indicates one or more errors were detected. The duration of the test is controlled by the pulse width
applied to the Des BISTEN pin.
Sample BIST Sequence
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