DS90UR908Q_14 Datasheet, PDF (20/33 Pages) Texas Instruments – 5 - 65 MHz 24-bit Color FPD-Link II to FPD-Link Converter

DS90UR908Q
SNLS317H – SEPTEMBER 2009 – REVISED APRIL 2013
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See Figure 19 for the BIST mode flow diagram.
Step 1: Place the DS90UR907Q or DS90UR905Q in BIST Mode by setting BISTEN = H. The BIST Mode is
enabled via the BISTEN pin. An RxCLKIN or PCLK is required for all the Ser options. When the DS90UR908Q
detects the BIST mode pattern and command (DCA and DCB code) the RGB and control signal outputs are shut
off.
Step 2: Place the DS90UR908Q in BIST mode by setting the BISTEN = H. The Device is now in the BIST mode
and checks the incoming serial payloads for errors. If an error in the payload (1 to 24) is detected, the PASS pin
will switch low for one half of the clock period. During the BIST test, the PASS output can be monitored and
counted to determine the payload error rate.
Step 3: To Stop the BIST mode, the DS90UR908Q BISTEN pin is set Low. It stops checking the data and the
final test result is held on the PASS pin. If the test ran error free, the PASS output will be High. If there was one
or more errors detected, the PASS output will be Low. The PASS output state is held until a new BIST is run, the
device is RESET, or Powered Down. The BIST duration is user controlled by the duration of the BISTEN signal.
Step 4: To return the link to normal operation, the serializer BISTEN input is set Low. The Link returns to normal
operation.
Figure 20 shows the waveform diagram of a typical BIST test for two cases. Case 1 is error free, and Case 2
shows one with multiple errors. In most cases it is difficult to generate errors due to the robustness of the link
(differential data transmission etc.), thus they may be introduced by greatly extending the cable length, faulting
the interconnect, reducing signal condition enhancements (De-Emphasis, VODSEL, or Rx Equalization).
Normal
Step 1: SER in BIST
BIST
Wait
Step 2: Wait, DES in BIST
BIST
Start
Step 3: DES in Normal
Mode - check PASS
BIST
Stop
Step 4: SER in Normal
Figure 19. BIST Mode Flow Diagram
20
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