DS90UR908Q_14 Datasheet, PDF (17/33 Pages) Texas Instruments – 5 - 65 MHz 24-bit Color FPD-Link II to FPD-Link Converter

DS90UR908Q
www.ti.com
SNLS317H – SEPTEMBER 2009 – REVISED APRIL 2013
Table 2. EQ Pin Configuration Table
EQ (Strap Option)
L
H
Effect
EQ = Off
~12 dB
POWER SAVING FEATURES
PowerDown Feature (PDB)
The DS90UR908Q has a PDB input pin to ENABLE or POWER DOWN the device. This pin can be controlled by
the system to save power, disabling the Des when the display is not needed. An auto detect mode is also
available. In this mode, the PDB pin is tied High and the Des will enter POWER DOWN when the serial stream
stops. When the serial stream starts up again, the Des will lock to the input stream and assert the LOCK pin and
output valid data. In POWER DOWN mode, the Data and PCLK output states are determined by the OSS_SEL
status. Note – in POWER DOWN, the optional Serial Bus Control Registers are RESET.
Stop Stream SLEEP Feature
The DS90UR908Q will enter a low power SLEEP state when the input serial stream is stopped. A STOP
condition is detected when the embedded clock bits are not present. When the serial stream starts again, the
Des will then lock to the incoming signal and recover the data. Note – in STOP STREAM SLEEP, the optional
Serial Bus Control Registers values are RETAINED.
OUTPUT INTERFACES (LVCMOS & FPD-LINK)
CLOCK-DATA RECOVERY STATUS FLAG (LOCK), OUTPUT ENABLE (OEN) and OUTPUT STATE SELECT (OSS_SEL)
When PDB is driven HIGH, the CDR PLL begins locking to the serial input, LOCK is Low and the FPD-Link
interface state is determined by the state of the OSS_SEL pin.
After the DS90UR908Q completes its lock sequence to the input serial data, the LOCK output is driven HIGH,
indicating valid data and clock recovered from the serial input is available on the FPD-Link outputs. The TxCLK
output is held at its current state at the change from OSC_CLK (if this is enabled via OSC_SEL) to the recovered
clock (or vice versa). Note that the FPD-Link outputs may be held in an inactive state (TRI-STATE) through the
use of the Output Enable pin (OEN).
If there is a loss of clock from the input serial stream, LOCK is driven Low and the state of the outputs are based
on the OSS_SEL setting (configuration pin or register).
PDB
L
L
H
H
H
H
INPUTS
OEN
X
X
L
H
L
H
Table 3. Output State Table
OSS_SEL
X
L
H
H
X
X
LOCK
X
L
L
L
H
H
OUTPUTS
OTHER OUTPUTS
TxCLKOUT is TRI-STATE
TxOUT[3:0] areTRI-STATE
PASS is TRI-STATE
TxCLKOUT is TRI-STATE
TxOUT[3:0] areTRI-STATE
PASS is HIGH
TxCLKOUT is TRI-STATE
TxOUT[3:0] areTRI-STATE
PASS is TRI-STATE
TxCLKOUT is TRI-STATE or OSC Output through Register bit
TxOUT[3:0] areTRI-STATE
PASS is TRI-STATE
TxCLKOUT is TRI-STATE
TxOUT[3:0] areTRI-STATE
PASS is HIGH
TxCLKOUT is Active
TxOUT[3:0] are Active
PASS is Active
(Normal operating mode)
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