DS90UR908Q_14 Datasheet, PDF (22/33 Pages) Texas Instruments – 5 - 65 MHz 24-bit Color FPD-Link II to FPD-Link Converter

DS90UR908Q
SNLS317H – SEPTEMBER 2009 – REVISED APRIL 2013
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SDA
SCL
S
START condition, or
START repeat condition
Figure 22. START and STOP Conditions
P
STOP condition
The third pin is the ID[X] pin. This pin sets one of five possible device addresses. Two different connections are
possible. The pin may be pulled to V_DD (1.8V, NOT V_DDIO)) with a 10 kΩ resistor. Or a 10 kΩ pull up resistor (to
V_DD1.8V, NOT V_DDIO)) and a pull down resistor of the recommended value to set other three possible addresses
may be used. See Table 7 for the Des. Do not tie ID[x] directly to ground.
The Serial Bus protocol is controlled by START, START-Repeated, and STOP phases. A START occurs when
SCL transitions Low while SDA is High. A STOP occurs when SDA transition High while SCL is also HIGH. See
Figure 22.
To communicate with a remote device, the host controller (master) sends the slave address and listens for a
response from the slave. This response is referred to as an acknowledge bit (ACK). If a slave on the bus is
addressed correctly, it Acknowledges (ACKs) the master by driving the SDA bus low. If the address doesn't
match a device's slave address, it Not-acknowledges (NACKs) the master by letting SDA be pulled High. ACKs
also occur on the bus when data is being transmitted. When the master is writing data, the slave ACKs after
every data byte is successfully received. When the master is reading data, the master ACKs after every data
byte is received to let the slave know it wants to receive another data byte. When the master wants to stop
reading, it NACKs after the last data byte and creates a stop condition on the bus. All communication on the bus
begins with either a Start condition or a Repeated Start condition. All communication on the bus ends with a Stop
condition. A READ is shown in Figure 23 and a WRITE is shown in Figure 24.
If the Serial Bus is not required, the three pins may be left open (NC).
Resistor
RID kΩ
(5%tol)
0.47
2.7
8.2
Open
Table 7. ID[x] Resistor Value
Address
7'b
7b' 111 0001 (h'71)
7b' 111 0010 (h'72)
7b' 111 0011 (h'73)
7b' 111 0110 (h'76)
Address
8'b
0 appended
(WRITE)
8b' 1110 0010 (h'E2)
8b' 1110 0100 (h'E4)
8b' 1110 0110 (h'E6)
8b' 1110 1100 (h'EC)
Slave Address
Register Address
S
A
2
A
1
A
0
a
0
c
k
a
c
k
S
Slave Address
a
A
2
A
1
A
0
1
c
k
Data
a
c
k
P
Figure 23. Serial Control Bus — READ
Slave Address
Register Address
S
A
2
A
1
A
0
a
0
c
k
a
c
k
Data
a
c
k
P
Figure 24. Serial Control Bus — WRITE
22
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