DS90UR908Q_14 Datasheet, PDF (18/33 Pages) Texas Instruments – 5 - 65 MHz 24-bit Color FPD-Link II to FPD-Link Converter

DS90UR908Q
SNLS317H – SEPTEMBER 2009 – REVISED APRIL 2013
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LVCMOS 1.8V / 3.3V VDDIO Operation
The LVCMOS outputs can operate with 1.8 V or 3.3 V levels (V_DDIO) for target (Display) compatibility. The 1.8 V
levels will offer a system power savings. This applies to the following pins: PASS and LOCK.
FPD-LINK OUTPUT
VODSEL
The differential output voltage of the FPD-Link interface is controlled by the VODSEL input.
VODSEL
L
H
Table 4. VODSEL Configuration Table
Result
VOD is 250mV TYP (500mVp-p)
VOD is 400mV TYP (800mVp-p)
SSCG GENERATION — OPTIONAL
The Des provides an internally generated spread spectrum clock (SSCG) to modulate its outputs. Both clock and
data outputs are modulated. This will aid to lower system EMI. Output SSCG deviations to ±2.0% (4% total) at up
to 35kHz modulations nominally are available. See Table 5 and Table 6. This feature may be controlled by pins
or by register. The LFMODE should be set appropriately if the SSCG is being used. Set LFMODE High if the
clock frequency is between 5 MHz and 20 MHz, set LFMODE Low if the clock frequency is between 20 MHz and
65 MHz.
SSC2
L
L
L
L
H
H
H
H
Table 5. SSCG Configuration (LFMODE = L) — Des Output
SSC[2:0] Inputs
LFMODE = L (20 - 65 MHz)
SSC1
L
L
H
H
L
L
H
H
SSC0
L
H
L
H
L
H
L
H
fdev (%)
OFF
±0.9
±1.2
±1.9
±2.3
±0.7
±1.3
±1.7
Result
fmod (kHz)
OFF
CLK/2168
CLK/1300
SSC2
L
L
L
L
H
H
H
H
Table 6. SSCG Configuration (LFMODE = H) — Des Output
SSC[2:0] Inputs
LFMODE = H (5 - 20 MHz)
SSC1
L
L
H
H
L
L
H
H
SSC0
L
H
L
H
L
H
L
H
fdev (%)
OFF
±0.7
±1.3
±1.8
±2.2
±0.7
±1.2
±1.7
Result
fmod (kHz)
OFF
CLK/625
CLK/385
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