DRV8302_16 Datasheet, PDF (8/32 Pages) Texas Instruments – Three Phase Gate Driver

DRV8302
SLES267C – AUGUST 2011 – REVISED MARCH 2016
www.ti.com
6.6 Gate Timing and Protection Characteristics
TIMING, OUTPUT PINS
t_pd,If-O
t_pd,Ir-O
T_{d_min}
Positive input falling to GH_x falling
Positive input rising to GL_x falling
Minimum dead time after hand
shaking ⁽¹⁾
T_dtp
Dead Time
t_GDr
Rise time, gate drive output
t_GDF
Fall time, gate drive output
T_{ON_MIN}
Minimum on pulse
T_{pd_match}
Propagation delay matching between
high side and low side
T_{dt_match}
Deadtime matching
TIMING, PROTECTION AND CONTROL
t_{pd,R_GATE-OP}
Start-up time, from EN_GATE active
high to device ready for normal
operation
t_{pd,R_GATE-Quick}
If EN_GATE goes from high to low and
back to high state within quick reset
time, it will only reset all faults and gate
driver without powering down charge
pump, current amp, and related internal
voltage regulators.
t_pd,E-L
t_pd,E-FAULT
OTW_CLR
Delay, error event to all gates low
Delay, error event to FAULT low
Junction temperature for resetting
overtemperature warning
OTW_SET/OTSD_C
LR
Junction temperature for
overtemperature warning and resetting
overtemperature shut down
OTSD_SET
Junction temperature for
overtemperature shut down
CL=1 nF, 50% to 50%
CL=1 nF, 50% to 50%
With R_DTC set to different values
CL=1 nF, 10% to 90%
CL=1 nF, 90% to 10%
Not including handshake communication.
Hiz to on state, output of gate driver
PVDD is up before start-up, all charge
pump caps and regulator caps as in
recommended condition
Maximum low pulse time
MIN NOM MAX UNIT
45
ns
45
ns
50 ns
50
500 ns
25
ns
25
ns
50 ns
5 ns
5 ns
5
10 ms
10 us
200
ns
200
ns
115
°C
130
°C
150
°C
(1) Dead time programming definition: Adjustable delay from GH_x falling edge to GL_X rising edge, and GL_X falling edge to GH_X rising
edge. This is a minimum dead-time insertion. It is not added to the value set by the microcontroller externally.
6.7 Current Shunt Amplifier Characteristics
T_C = 25°C unless otherwise specified
PARAMETER
TEST CONDITIONS
G1
Gain option 1
(GAIN = 0 V)
G2
Gain option 2
(GAIN = 2 V)
Tsettling Settling time to 1%
Tc = 0°C to 60°C, G = 10, Vstep = 2 V
Tsettling Settling time to 1%
Tc = 0°C to 60°C, G = 40, Vstep = 2 V
Vswing
Output swing linear range
Slew Rate
G = 10
DC_offset Offset error RTI
G = 10 with input shorted
Drift_offset Offset drift RTI
Ibias
Input bias current
Vin_com Common input mode range
Vin_dif
Differential input range
Vo_bias
Output bias
With zero input current, Vref up to 6 V
CMRR_OV
Overall CMRR with gain resistor
mismatch
CMRR at DC, gain = 10
MIN
TYP
9.5
10
38
40
300
1.2
0.3
10
10
–0.15
–0.3
–0.5%
0.5×Vref
MAX
10.5
42
5.7
4
100
0.15
0.3
0.5%
UNIT
V/V
V/V
ns
µs
V
V/µs
mV
µV/C
µA
V
V
V
70
85
dB
8
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