DRV8302_16 Datasheet, PDF (3/32 Pages) Texas Instruments – Three Phase Gate Driver

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5 Pin Configuration and Functions
DRV8302
SLES267C – AUGUST 2011 – REVISED MARCH 2016
DCA Package
56-Pin HTSSOP With PowerPAD™
Top View
RT_CLK 1
COMP 2
VSENSE 3
PWRGD 4
nOCTW 5
nFAULT 6
DTC 7
M_PWM 8
M_OC 9
GAIN 10
OC_ADJ 11
DC_CAL 12
GVDD 13
CP1 14
CP2 15
EN_GATE 16
INH_A 17
INL_A 18
INH_B 19
INL_B 20
INH_C 21
INL_C 22
DVDD 23
REF 24
SO1 25
SO2 26
AVDD 27
AGND 28
56 SS_TR
55 EN_BUCK
54 PVDD2
53 PVDD2
52 BST_BK
51 PH
50 PH
49 BIAS
48 BST_A
47 GH_A
46 SH_A
45 GL_A
44 SL_A
43 BST_B
42 GH_B
41 SH_B
40 GL_B
39 SL_B
38 BST_C
37 GH_C
36 SH_C
35 GL_C
34 SL_C
33 SN1
32 SP1
31 SN2
30 SP2
29 PVDD1
PIN
NO.
NAME
1
RT_CLK
2
COMP
3
VSENSE
4
PWRGD
5
nOCTW
6
nFAULT
7
DTC
8
M_PWM
9
M_OC
10
GAIN
11
OC_ADJ
12
DC_CAL
Pin Functions
I/O ⁽¹⁾
DESCRIPTION
I
Resistor timing and external clock for buck regulator. Resistor should connect to GND (PowerPAD™)
with very short trace to reduce the potential clock jitter due to noise.
O Buck error amplifier output and input to the output switch current comparator.
I
Buck output voltage sense pin. Inverting node of error amplifier.
I
An open drain output with external pullup resistor required. Asserts low if buck output voltage is low
due to thermal shutdown, dropout, overvoltage, or EN_BUCK shut down
O
Overcurrent and overtemperature warning indicator. This output is open drain with external pullup
resistor required.
O Fault report indicator. This output is open drain with external pullup resistor required.
I
Dead-time adjustment with external resistor to GND
Mode selection pin for PWM input configuration. If M_PWM = LOW, the device supports 6 independent
I
PWM inputs. When M_PWM = HIGH, the device must be connected to ONLY 3 PWM input signals on
INH_x. The complementary PWM signals for low side signaling will be internally generated from the
high side inputs.
Mode selection pin for over-current protection options. If M_OC = LOW, the gate driver will operate in a
I
cycle-by-cycle current limiting mode. If M_OC = HIGH, the gate driver will shutdown the channel which
detected an over-current event.
O
Gain selection for integrated current shunt amplifiers. If GAIN = LOW, the internal current shunt
amplifiers have a gain of 10V/V. If GAIN = HIGH, the current shunt amplifiers have a gain of 40V/V.
I
Overcurrent trip set pin. Apply a voltage on this pin to set the trip point for the internal overcurrent
protection circuitry. A voltage divider from DVDD is recommended.
I
When DC_CAL is high, device shorts inputs of shunt amplifiers and disconnects loads. DC offset
calibration can be done through external microcontroller.
(1) KEY: I =Input, O = Output, P = Power
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