DRV8302_16 Datasheet, PDF (17/32 Pages) Texas Instruments – Three Phase Gate Driver

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DRV8302
SLES267C – AUGUST 2011 – REVISED MARCH 2016
7.3.4.1.2 OC Latch Shutdown Mode
When an overcurrent event occurs, both the high-side and low-side MOSFETs will be disabled in the
corresponding half-bridge. The nFAULT pin will latch until the fault is reset through a quick EN_GATE reset
pulse.
7.3.4.2 OC_ADJ
When external MOSFET is turned on, the output current flows through the on resistance, R_DS(on) of the MOSFET,
which creates a voltage drop V_DS. The over current protection event will be enabled when the V_DS exceeds a pre-
set value. The voltage on OC_ADJ pin will be used to pre-set the OC tripped value. The OC tripped value I_OC
has to meet following equations:
R2
(R1 + R2) ^{´ DVDD = VDS}
where
• R1 + R2 ≥ 1 KΩ
• DVDD = 3.3 V
(3)
I_OC
=
V_DS
R_{DS(on )}
(4)
Connect OC_ADJ pin to DVDD to disable the over-current protection feature.
DVDD
R1
V_OC
OC_ADJ
R2
Figure 5. OC_ADJ Current Programming Pin Connection
7.3.4.3 Undervoltage Protection (UVLO)
To protect the power output stage during start-up, shutdown, and other possible undervoltage conditions, the
DRV8302 provides undervoltage protection by driving the gate drive outputs (GH_X, GL_X) low whenever PVDD
or GVDD are below their undervoltage thresholds (PVDD_UV/GVDD_UV). This will put the external MOSFETs in
a high impedance state.
A specific PVDD1 undervoltage transient brownout from 13 to 15 µs can cause the DRV8302 to become
unresponsive to external inputs until a full power cycle. The transient condition consists of having PVDD1 greater
than the PVDD_UV level and then PVDD1 dropping below the PVDD_UV level for a specific period of 13 to 15
µs. Transients shorter or longer than 13 to 15 µs will not affect the normal operation of the undervoltage
protection. Additional bulk capacitance can be added to PVDD1 to reduce undervoltage transients.
7.3.4.4 Overvoltage Protection (GVDD_OV)
The device will shut down both the gate driver and charge pump if the GVDD voltage exceeds the GVDD_OV
threshold to prevent potential issues related to the GVDD pin or the charge pump (For example, short of external
GVDD cap or charge pump). The fault is a latched fault and can only be reset through a reset transition on the
EN_GATE pin.
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