DRV8302_16 Datasheet, PDF (16/32 Pages) Texas Instruments – Three Phase Gate Driver

DRV8302
SLES267C – AUGUST 2011 – REVISED MARCH 2016
www.ti.com
Table 4. Buck Regulator External Components
NAME
R_{RT_CLK}
C_COMP
RC_COMP
R_VSENSE1
R_VSENSE2
R_PWRGD
L_PH
D_PH
C_PH
C_{BST_BK}
C_PVDD2
C_{SS_TR}
PIN 1
RT_CLK
COMP
COMP
PH (Filtered)
VSENSE
PWRGD
PH
PH
PH (Filtered)
BST_BK
PVDD2
SS_TR
PIN 2
GND (PowerPAD)
GND (PowerPAD)
GND (PowerPAD)
VSENSE
GND (PowerPAD)
V_CC ⁽¹⁾
PH (Filtered)
GND (PowerPAD)
GND (PowerPAD)
PH
GND (PowerPAD)
GND (PowerPAD)
RECOMMENDED
See Buck Converter
See Buck Converter
See Buck Converter
See Buck Converter
See Buck Converter
≥ 10 kΩ
See Buck Converter
See Buck Converter
See Buck Converter
See Buck Converter
≥4.7 µF (20%) ceramic, rated for PVDD2
See Buck Converter
(1) V_CC is the logic supply to the MCU
7.3.4 Protection Features
The DRV8302 provides a broad range of protection features and fault condition reporting. The DRV8302 has
undervoltage and overtemperature protection for the IC. It also has overcurrent and undervoltage protection for
the MOSFET power stage. In fault shut down conditions all gate driver outputs is held low to ensure the external
MOSFETs are in a high impedance state.
7.3.4.1 Overcurrent Protection (OCP) and Reporting
To protect the power stage from damage due to excessive currents, V_DS sensing circuitry is implemented in the
DRV8302. Based on the R_DS(on) of the external MOSFETs and the maximum allowed I_DS, a voltage threshold can
be determined to trigger the overcurrent protection features when exceeded. The voltage threshold is
programmed through the OC_ADJ pin by applying an external reference voltage with a DAC or resistor divider
from DVDD. Overcurrent protection should be used as a protection scheme only; it is not intended as a precise
current regulation scheme. There can be up to a 20% tolerance across channels for the V_DS trip point.
V_DS = I_DS ´ R_DS(on)
(2)
The V_DS sense circuit measures the voltage from the drain to the source of the external MOSFET while the
MOSFET is enabled. The high-side sense is between the PVDD and SH_X pins. The low-side sense is between
the SH_X and SL_X pins. Ensuring a differential, low impedance connection to the external MOSFETs for these
lines helps provide accurate V_DS sensing.
There are two different overcurrent modes that can be set through the M_OC pin.
7.3.4.1.1 Current Limit Mode (M_OC = LOW)
In current limit mode the devices uses current limiting instead of device shutdown during an overcurrent event.
After the overcurrent event, the MOSFET in which the overcurrent was detected in will shut off until the next
PWM cycle. The overcurrent event will be reported through the nOCTW pin. The nOCTW pin will be held low for
a maximum 64 µs period (internal timer) or until the next PWM cycle. If another overcurrent event is triggered
from another MOSFET, during a previous overcurrent event, the reporting will continue for another 64 µs period
(internal timer will restart) or until both PWM signals cycle.
In current limit mode the device uses current limiting instead of device shutdown during an overcurrent event. In
this mode the device reports overcurrent events through the nOCTW pin. The nOCTW pin will be held low for a
maximum 64 µs period (internal timer) or until the next PWM cycle. If another overcurrent event is triggered from
another MOSFET, during a previous overcurrent event, the reporting will continue for another 64 µs period
(internal timer will restart) or until both PWM signals cycle.
16
Submit Documentation Feedback
Product Folder Links: DRV8302
Copyright © 2011–2016, Texas Instruments Incorporated