DRV8302_16 Datasheet, PDF (15/32 Pages) Texas Instruments – Three Phase Gate Driver

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DRV8302
SLES267C – AUGUST 2011 – REVISED MARCH 2016
7.3.3 Buck Converter
The DRV8302 uses an integrated TPS54160 1.5-A, 60-V, step-down DC-DC converter. Although integrated in
the same device, the buck converter is designed completely independent of the rest of the gate driver circuitry.
Because the buck converter can support external MCU or other external power need, the independency of buck
operation is crucial for a reliable system; this gives the buck converter minimum impact from gate driver
operations. Some examples are: when gate driver shuts down due to any failure, the buck still operates unless
the fault is coming from the buck itself. The buck keeps operating at much lower PVDD of 3.5 V, assuring the
system has a smooth power-up and power-down sequence when gate driver is not able to operate due to a low
PVDD.
For proper selection of the buck converter external components, see the data sheet, TPS54160 1.5-A, 60-V,
Step-Down DC/DC Converter With Eco-mode™, SLVSB56.
The buck has an integrated high-side N-channel MOSFET. To improve performance during line and load
transients the device implements a constant frequency, current mode control which reduces output capacitance
and simplifies external frequency compensation design.
The wide switching frequency of 300 kHz to 2200 kHz allows for efficiency and size optimization when selecting
the output filter components. The switching frequency is adjusted using a resistor to ground on the RT_CLK pin.
The device has an internal phase lock loop (PLL) on the RT_CLK pin that is used to synchronize the power
switch turn on to a falling edge of an external system clock.
The buck converter has a default start-up voltage of approximately 2.5 V. The EN_BUCK pin has an internal
pullup current source that can be used to adjust the input voltage undervoltage lockout (UVLO) threshold with
two external resistors. In addition, the pullup current provides a default condition. When the EN_BUCK pin is
floating the device will operate. The operating current is 116 µA when not switching and under no load. When the
device is disabled, the supply current is 1.3 µA.
The integrated 200-mΩ high-side MOSFET allows for high-efficiency power supply designs capable of delivering
1.5 A of continuous current to a load. The bias voltage for the integrated high side MOSFET is supplied by a
capacitor on the BOOT to PH pin. The boot capacitor voltage is monitored by an UVLO circuit that turns the high
side MOSFET off when the boot voltage falls below a preset threshold. The buck can operate at high duty cycles
because of the boot UVLO. The output voltage can be stepped down to as low as the 0.8-V reference.
The BUCK has a power good comparator (PWRGD) which asserts when the regulated output voltage is less
than 92% or greater than 109% of the nominal output voltage. The PWRGD pin is an open-drain output that
deasserts when the VSENSE pin voltage is between 94% and 107% of the nominal output voltage, allowing the
pin to transition high when a pullup resistor is used.
The BUCK minimizes excessive output overvoltage (OV) transients by taking advantage of the OV power good
comparator. When the OV comparator is activated, the high-side MOSFET is turned off and masked from turning
on until the output voltage is lower than 107%.
The SS_TR (slow start/tracking) pin is used to minimize inrush currents or provide power supply sequencing
during power-up. A small value capacitor should be coupled to the pin to adjust the slow start time. A resistor
divider can be coupled to the pin for critical power supply sequencing requirements. The SS_TR pin is
discharged before the output powers up. This discharging ensures a repeatable restart after an overtemperature
fault,
The BUCK, also, discharges the slow-start capacitor during overload conditions with an overload recovery circuit.
The overload recovery circuit slow-starts the output from the fault voltage to the nominal regulation voltage once
a fault condition is removed. A frequency foldback circuit reduces the switching frequency during start-up and
overcurrent fault conditions to help control the inductor current.
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