DRV8302_16 Datasheet, PDF (18/32 Pages) Texas Instruments – Three Phase Gate Driver

DRV8302
SLES267C – AUGUST 2011 – REVISED MARCH 2016
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7.3.4.5 Overtemperature Protection
A two-level overtemperature detection circuit is implemented:
• Level 1: overtemperature warning (OTW)
OTW is reported through nOCTW pin.
• Level 2: overtemperature (OT) latched shut down of gate driver and charge pump (OTSD_GATE)
Fault will be reported to nFAULT pin. This is a latched shut down, so gate driver will not be recovered
automatically even if OT condition is not present anymore. An EN_GATE reset through pin is required to
recover gate driver to normal operation after temperature goes below a preset value, t_{OTSD_CLR}.
7.3.4.6 Fault and Protection Handling
The nFAULT pin indicates an error event with shut down has occurred such as over-current, overtemperature,
overvoltage, or undervoltage. Note that nFAULT is an open-drain signal. nFAULT goes high when gate driver is
ready for PWM signal (internal EN_GATE goes high) during start-up.
The nOCTW pin indicates an overtemperature or over current event that is not necessarily related to shut down.
Following is the summary of all protection features and their reporting structure:
EVENT
PVDD
undervoltage
DVDD
undervoltage
GVDD
undervoltage
GVDD
overvoltage
OTW
OTSD_GATE
OTSD_BUCK
Buck output
undervoltage
Buck overload
External FET
overload – current limit
mode
External FET
overload – Latch mode
External FET
overload – reporting only
mode
Table 5. Fault and Warning Reporting and Handling
ACTION
External FETs HiZ;
Weak pulldown of all gate
driver output
External FETs HiZ;
Weak pulldown of all gate
driver output; When recovering,
reset all status registers
External FETs HiZ;
Weak pulldown of all gate
driver output
External FETs HiZ;
Weak pulldown of all gate driver output
Shut down the charge pump
Won’t recover and reset through
SPI reset command or
quick EN_GATE toggling
None
Gate driver latched shut down.
Weak pulldown of all gate driver output
to force external FETs HiZ
Shut down the charge pump
OTSD of Buck
LATCH
N
REPORTING ON
nFAULT PIN
Y
N
Y
N
Y
Y
Y
N
N
Y
Y
Y
N
UVLO_BUCK: auto-restart
N
Y, in PWRGD pin
Buck current limiting
(HiZ high side until current reaches
N
N
zero and then auto-recovering)
External FETs current Limiting
(only OC detected FET)
N
N
Weak pulldown of gate driver
output and PWM logic “0” of
LS and HS in the same phase.
Y
Y
External FETs HiZ
Reporting only
N
N
REPORTING ON
nOCTW PIN
N
N
N
N
Y
Y
N
N
N
Y
Y
Y
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