DRV8302_16 Datasheet, PDF (25/32 Pages) Texas Instruments – Three Phase Gate Driver

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10 Layout
DRV8302
SLES267C – AUGUST 2011 – REVISED MARCH 2016
10.1 Layout Guidelines
Use these layout recommendations when designing a PCB for the DRV8302.
• The DRV8302 makes an electrical connection to GND through the PowerPAD. Always check to ensure that
the PowerPAD has been properly soldered (See the application report, PowerPAD™ Thermally Enhanced
Package application report, SLMA002).
• PVDD bypass capacitors should be placed close to their corresponding pins with a low impedance path to
device GND (PowerPAD).
• GVDD bypass capacitor should be placed close its corresponding pin with a low impedance path to device
GND (PowerPAD).
• AVDD and DVDD bypass capacitors should be placed close to their corresponding pins with a low impedance
path to the AGND pin. It is preferable to make this connection on the same layer.
• AGND should be tied to device GND (PowerPAD) through a low impedance trace/copper fill.
• Add stitching vias to reduce the impedance of the GND path from the top to bottom side.
• Try to clear the space around and underneath the DRV8302 to allow for better heat spreading from the
PowerPAD.
10.2 Layout Example
GND
VCC
RT_CLK 1
COMP 2
VSENSE 3
PWRGD 4
nOCTW 5
nFAULT 6
1
DTC 7
M_PWM 8
M_OC 9
GAIN 10
OC_ADJ 11
DC_CAL 12
0.1 µF
GVDD 13
0.022 µF
CP1 14
CP2 15
EN_GATE 16
INH_A 17
INL_A 18
INH_B 19
INL_B 20
INH_C 21
INL_C 22
1 µF
DVDD 23
REF 24
SO1 25
SO2 26
1 µF
AVDD 27
AGND 28
GND
GND
VCC
47 µF
0.015 µF
56 SS_TR ^{4.7 µF 0.1 µF}
55 EN_BUCK
54 PVDD2
53 PVDD2
52 BST_BK ^{0.1 µF}
51 PH
50 PH
49 BIAS
1M
48 BST_A ^{0.1 µF}
47 GH_A
46 SH_A
45 GL_A
44 SL_A
43 BST_B ^{0.1 µF}
42 GH_B
41 SH_B
40 GL_B
39 SL_B
38 BST_C ^{0.1 µF}
37 GH_C
36 SH_C
35 GL_C
34 SL_C
1000 pF
33 SN1
32 SP1
1000 pF
31 SN2
30 SP2
29 PVDD1 ^{4.7 µF 0.1 µF}
22 µH
Legend
GND
Top Layer
Bottom Layer
Via
GND
220 µF
PVDD
10
D
2.2 µF
D
D
D
S
10 m
S
S
G
10
10
D
2.2 µF
D
D
D
S
10 m
S
S
G
10
10
D
2.2 µF
D
D
D
S
S
S
G
10
220 µF
G
S
S
OUTA
S
D
D
D
D
G
S
S
OUTB
S
D
D
D
D
G
S
S
OUTC
S
D
D
D
D
Figure 12. Top and Bottom Layer Layout Schematic
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