MSP430F643 Datasheet, PDF (76/106 Pages) Texas Instruments – MIXED SIGNAL MICROCONTROLLER

MSP430F643x
SLAS720B – AUGUST 2010 – REVISED AUGUST 2012
www.ti.com
LDO-PWR (LDO Power System)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
V_LAUNCH
V_LDOI
V_LDO
V_{LDO_EXT}
PARAMETER
LDO input detection threshold
LDO input voltage
LDO output voltage
LDOO terminal input voltage with LDO
disabled
TEST CONDITIONS
Normal operation
LDO disabled
V_CC
MIN TYP
3.76
3.3
1.8
I_LDOO
I_DET
C_LDOI
C_LDOO
t_ENABLE
Maximum external current from LDOO terminal LDO is on
LDO current overload detection⁽¹⁾
LDOI terminal recommended capacitance
LDOO terminal recommended capacitance
Settling time V_LDO
Within 2%,
recommended capacitances
60
4.7
220
(1) A current overload is detected when the total current supplied from the LDO exceeds this value.
MAX
3.75
5.5
±9%
UNIT
V
V
V
3.6 V
20 mA
100 mA
µF
nF
2 ms
Flash Memory
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST
CONDITIONS
MIN TYP
DV_{CC(PGM/ERASE)} Program and erase supply voltage
I_PGM
Average supply current from DVCC during program
I_ERASE
Average supply current from DVCC during erase
I_MERASE, I_BANK
Average supply current from DVCC during mass erase or bank
erase
t_CPT
Cumulative program time
Program and erase endurance
See ⁽¹⁾
1.8
3
10⁴
10⁵
t_Retention
t_Word
t_{Block, 0}
Data retention duration
Word or byte program time
Block program time for first byte or word
T_J = 25°C
100
See ⁽²⁾
64
See ⁽²⁾
49
t_{Block, 1–(N–1)}
Block program time for each additional byte or word, except for last
byte or word
See ⁽²⁾
37
t_{Block, N}
Block program time for last byte or word
See ⁽²⁾
55
t_{Seg Erase}
Erase time for segment, mass erase, and bank erase when
available
See ⁽²⁾
23
f_MCLK,MGR
MCLK frequency in marginal read mode
(FCTL4.MGR0 = 1 or FCTL4.MGR1 = 1)
0
MAX UNIT
3.6 V
5 mA
2.5 mA
2 mA
16 ms
cycles
years
85 µs
65 µs
49 µs
73 µs
32 ms
1 MHz
(1) The cumulative program time must not be exceeded when writing to a 128-byte flash block. This parameter applies to all programming
methods: individual word or byte write and block write modes.
(2) These values are hardwired into the flash controller's state machine.
JTAG and Spy-Bi-Wire Interface
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST
CONDITIONS
MIN TYP
f_SBW
t_SBW,Low
t_{SBW, En}
Spy-Bi-Wire input frequency
Spy-Bi-Wire low clock pulse duration
Spy-Bi-Wire enable time (TEST high to acceptance of first clock
edge) ⁽¹⁾
2.2 V, 3 V
2.2 V, 3 V
2.2 V, 3 V
0
0.025
t_SBW,Rst
Spy-Bi-Wire return to normal operation time
15
MAX UNIT
20 MHz
15 µs
1 µs
100 µs
(1) Tools that access the Spy-Bi-Wire interface must wait for the t_SBW,En time after pulling the TEST/SBWTCK pin high before applying the
first SBWTCK clock edge.
76
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