MSP430F643 Datasheet, PDF (71/106 Pages) Texas Instruments – MIXED SIGNAL MICROCONTROLLER

MSP430F643x
www.ti.com
SLAS720B – AUGUST 2010 – REVISED AUGUST 2012
12-Bit DAC, Reference Input Specifications
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
VeREF+
Reference input voltage
range
TEST CONDITIONS
DAC12IR = 0^{(1) (2)}
DAC12IR = 1^{(3) (4)}
V_CC
2.2 V, 3 V
MIN TYP
AV_CC
/3
AV_CC
Ri_(VREF+),
Ri_(VeREF+)
Reference input resistance⁽⁵⁾
DAC12_0 IR = DAC12_1 IR = 0
DAC12_0 IR = 1, DAC12_1 IR = 0
DAC12_0 IR = 0, DAC12_1 IR = 1
DAC12_0 IR = DAC12_1 IR = 1,
DAC12_0 SREFx = DAC12_1 SREFx⁽⁶⁾
2.2 V, 3 V
20
48
48
24
MAX
AV_CC
+ 0.2
AV_CC
+ 0.2
UNIT
V
MΩ
kΩ
(1) For a full-scale output, the reference input voltage can be as high as 1/3 of the maximum output voltage swing (AVCC).
(2) The maximum voltage applied at reference input voltage terminal VeREF+ = [AV_CC – V_E(O)] / [3 × (1 + E_G)].
(3) For a full-scale output, the reference input voltage can be as high as the maximum output voltage swing (AVCC).
(4) The maximum voltage applied at reference input voltage terminal VeREF+ = [AV_CC – V_E(O)] / (1 + E_G).
(5) This impedance depends on tradeoff in power savings. Current devices have 48 kΩ for each channel when divide is enabled. Can be
increased if performance can be maintained.
(6) When DAC12IR = 1 and DAC12SREFx = 0 or 1 for both channels, the reference input resistive dividers for each DAC are in parallel
reducing the reference input resistance.
12-Bit DAC, Dynamic Specifications
V_REF = V_CC, DAC12IR = 1 (see Figure 19 and Figure 20), over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)
PARAMETER
t_ON
DAC12 on time
TEST CONDITIONS
DAC12_xDAT = 800h,
Error_V(O) < ±0.5 LSB⁽¹⁾
(see Figure 19)
DAC12AMPx = 0 → {2, 3, 4}
DAC12AMPx = 0 → {5, 6}
DAC12AMPx = 0 → 7
V_CC
2.2 V, 3 V
MIN TYP MAX UNIT
60 120
15
30 µs
6
12
t_S(FS) Settling time, full scale
DAC12_xDAT =
80h → F7Fh → 80h
DAC12AMPx = 2
DAC12AMPx = 3, 5
DAC12AMPx = 4, 6, 7
2.2 V, 3 V
100 200
40
80 µs
15
30
t_S(C-C)
Settling time, code to
code
DAC12_xDAT =
3F8h → 408h → 3F8h,
BF8h → C08h → BF8h
DAC12AMPx = 2
DAC12AMPx = 3, 5
DAC12AMPx = 4, 6, 7
2.2 V, 3 V
5
2
µs
1
SR Slew rate
DAC12_xDAT =
80h → F7Fh → 80h⁽²⁾
DAC12AMPx = 2
DAC12AMPx = 3, 5
DAC12AMPx = 4, 6, 7
2.2 V, 3 V
0.05 0.35
0.35 1.10
1.50 5.20
V/µs
Glitch energy
DAC12_xDAT =
800h → 7FFh → 800h
DAC12AMPx = 7
2.2 V, 3 V
35
nV-s
(1) R_Load and C_Load connected to AV_SS (not AV_CC/2) in Figure 19.
(2) Slew rate applies to output voltage steps ≥ 200 mV.
DAC Output
R_O/P(DAC12.x)
R_Load = 3 kW
I_Load
AV_CC
2
C_Load = 100 pF
Conversion 1 Conversion 2
V_OUT
Glitch
Energy
±1/2 LSB
Conversion 3
±1/2 LSB
t_settleLH
Figure 19. Settling Time and Glitch Energy Testing
t_settleHL
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